A method includes etching a hybrid substrate to form a recess extending into the hybrid substrate. The hybrid substrate includes a first semiconductor layer having a first surface orientation, a dielectric layer over the first semiconductor layer, and a second semiconductor layer having a second surface orientation different from the first surface orientation. After the etching, a top surface of the first semiconductor layer is exposed to the recess. A spacer is formed on a sidewall of the recess. The spacer contacts a sidewall of the dielectric layer and a sidewall of the second semiconductor layer. An epitaxy is performed to grow an epitaxy semiconductor region from the first semiconductor layer. The spacer is removed.

Systems and methods are described herein to include an epitaxial metal layer between a rare earth oxide and a semiconductor layer. Systems and methods are described to grow a layered structure, comprising a substrate, a first rare earth oxide layer epitaxially grown over the substrate, a first metal layer epitaxially grown over the rare earth oxide layer, and a first semiconductor layer epitaxially grown over the first metal layer. Specifically, the substrate may include a porous portion, which is usually aligned with the metal layer, with or without a rare earth oxide layer in between.

A method for manufacturing a bonded SOI wafer, the method using a silicon single crystal wafer having a resistivity of 100 Ω.Math.cm or more as the base wafer, and including steps of: forming an underlying insulator film on a bonding surface side of the base wafer; depositing a polycrystalline silicon layer on a surface of the underlying insulator film; polishing a surface of the polycrystalline silicon layer; modifying the polycrystalline silicon layer by performing ion implantation on the polished polycrystalline silicon layer to form a modified silicon layer; forming the insulator film on a bonding surface of the bond wafer; bonding the bond wafer and a surface of the modified silicon layer of the base wafer with the insulator film interposed therebetween; and thinning the bonded bond wafer to form an SOI layer. This provides a bonded SOI wafer excellent in harmonic wave characteristics.

Methods and systems for selectively depositing a p-type doped silicon germanium layer and structures and devices including a p-type doped silicon germanium layer are disclosed. An exemplary method includes providing a substrate, comprising a surface comprising a first area comprising a first material and a second area comprising a second material, within a reaction chamber; depositing a p-type doped silicon germanium layer overlying the surface, the p-type doped silicon germanium layer comprising gallium; and depositing a cap layer overlying the p-type doped silicon germanium layer. The method can further include an etch step to remove the cap layer and the p-type doped silicon germanium layer overlying the second material.

A wafer carrier includes a pocket sized and shaped to accommodate a wafer, the pocket having a base and a substantially circular perimeter, and a removable orientation marker, the removable orientation marker comprising an outer surface and an inner surface, the outer surface having an arcuate form sized and shaped to mate with the substantially circular perimeter of the pocket, and the inner surface comprising a flat face, wherein the removable orientation marker further comprises a notch at a first end of the flat face.

The invention relates to a process for the preparation of a semiconductor material comprising at least one entirely monocrystalline semiconductor layer, said process comprising the steps of preparation of the surface of a first substrate to receive a monocrystalline silicon layer; deposition by Plasma-Enhanced Chemical Vapor Deposition (PECVD) of a layer of monocrystalline silicon by epitaxial growth with a growth rate gradient on the silicon layer monocrystalline obtained in step (i); and epitaxial growth of a monocrystalline layer of a semiconductor material on the monocrystalline silicon layer obtained in step (ii), to thus obtain a material comprising at least one entirely monocrystalline semiconductor layer. The invention also relates to a multilayer material comprising a monocrystalline layer of semiconductor material.

Embodiments of the invention include a semiconductor device having a fin-shaped channel with a bottom surface, sidewalls and a top surface. A first source or drain (S/D) region is communicatively coupled to the fin-shaped channel, and a sub-channel region is between the bottom surface of the fin-shaped channel and a substrate. A U-shaped dielectric region within a first portion of the sub-channel region, wherein the U-shaped dielectric region includes a bottom isolation layer and a first inner spacer region. A wrap-around gate structure extends around the bottom surface, the sidewalls and the top surface of the fin-shaped channel, wherein a bottom region of the wrap-around gate structure is within a second portion of the sub-channel region.

The present invention provides a GaN/two-dimensional AlN heterojunction rectifier on a silicon substrate and a preparation method therefor and belongs to the field of rectifiers. The rectifier comprises a silicon substrate, a GaN buffer layer, a carbon-doped semi-insulating GaN layer, a two-dimensional AlN layer, a non-doped GaN layer, a non-doped InGaN layer and a SiN.sub.x passivation layer that are stacked in sequence. The rectifier further comprises a mesa isolation groove and a Schottky contact electrode that are arranged at one side. The mesa isolation groove is in contact with the non-doped GaN layer, the non-doped InGaN layer, the SiN.sub.x passivation layer and the Schottky contact electrode. The Schottky contact electrode is in contact with the mesa isolation groove and the non-doped GaN layer. The thickness of the two-dimensional AlN layer is only several atomic layers, thus the received stress and polarization intensity are greater than those of the AlGaN layer.

A III-nitride-based semiconductor wafer is provided that includes a substrate with a central region and a peripheral edge region. One or more intermediate layers may be optionally provided selected from a buffer layer, a seed layer, or a transition layer. A peripheral edge feature is formed in or on a peripheral edge region of the substrate or the transition layer, with one or more peripheral edge passivation layers or peripheral edge surface texturing. The peripheral edge feature extends only around the peripheral edge and not in the central region. One or more III-nitride-based layers is positioned over the central region. In the central region, the III-nitride layer is an epitaxial layer while in the peripheral edge region, it is a polycrystalline layer. Stress due to lattice mismatches and differences in the coefficient of thermal expansion between the III-nitride layer and the substrate is relieved, minimizing defects.

A method for producing a nitride compound semiconductor component is disclosed. In an embodiment the method includes providing a growth substrate, growing a nucleation layer of an aluminum-containing nitride compound semiconductor onto the growth substrate, growing a tension layer structure for generating a compressive stress, wherein the tension layer structure comprises at least a first GaN semiconductor layer and a second GaN semiconductor layer, and wherein an Al(Ga)N interlayer for generating the compressive stress is disposed between the first GaN semiconductor layer and the second GaN semiconductor layer and growing a functional semiconductor layer sequence of the nitride compound semiconductor component onto the tension layer structure, wherein a growth of the second GaN semiconductor layer is preceded by a growth of a first 3D AlGaN layer on the Al(Ga)N interlayer in such a way that it has nonplanar structures.