A method for producing a GaN crystal is provided. In the method, front surfaces of a plurality of tiling GaN seeds closely arranged side by side on a flat surface of a plate are planarized. An aggregated seed is formed by arranging the tiling GaN seeds closely side by side on a susceptor of an HVPE apparatus in the same arrangement as when fixed on the plate, with the front planarized surfaces facing upward. A bulk GaN crystal is grown epitaxially on the aggregated seed by an HVPE method.

A light emitting heterostructure including one or more fine structure regions is provided. The light emitting heterostructure can include a plurality of barriers alternating with a plurality of quantum wells. One or more of the barriers and/or quantum wells includes a fine structure region. The fine structure region includes a plurality of subscale features arranged in at least one of: a growth or a lateral direction.

Implementations described herein generally relate to methods for relaxing strain in thin semiconductor films grown on another semiconductor substrate that has a different lattice constant. Strain relaxation typically involves forming a strain relaxed buffer layer on the semiconductor substrate for further growth of another semiconductor material on top. Whereas conventionally formed buffer layers are often thick, rough and/or defective, the strain relaxed buffer layers formed using the implementations described herein demonstrate improved surface morphology with minimal defects.

A technique of improving the breakdown voltage of a semiconductor device is provided. There is provided a method of manufacturing a semiconductor device comprising a process of forming a p-type semiconductor layer that contains a p-type impurity and has a dislocation density of not higher than 1.0×10.sup.7 cm.sup.−2, on an n-type semiconductor layer that contains an n-type impurity and has a dislocation density of not higher than 1.0×10.sup.7 cm.sup.−2; an n-type semiconductor region forming process of forming an n-type semiconductor region in at least part of the p-type semiconductor layer by ion-implanting an n-type impurity into the p-type semiconductor layer and performing heat treatment to activate the ion-implanted n-type impurity; and a process of forming a trench that is recessed to pass through the p-type semiconductor layer and reach the n-type semiconductor layer. In the n-type semiconductor region forming process, a p-type impurity diffusion region in which the p-type impurity contained in the p-type semiconductor layer is diffused is formed in at least part of the n-type semiconductor layer that is located below the n-type semiconductor region.

A method for the reuse of gallium nitride (GaN) epitaxial substrates uses band-gap-selective photoelectrochemical (PEC) etching to remove one or more epitaxial layers from bulk or free-standing GaN substrates without damaging the substrate, allowing the substrate to be reused for further growth of additional epitaxial layers. The method facilitates a significant cost reduction in device production by permitting the reuse of expensive bulk or free-standing GaN substrates.

When a defect region is present near the pn junction in a GaN layer, lattice defects are present in the depletion layer. Therefore, when a reverse bias is applied to the pn junction, the defects in the depletion layer cause the generated current to flow as a leakage current. The leakage current flowing through the depletion layer can cause a decrease in the withstand voltage at the pn junction. Provided is a semiconductor device using gallium nitride, including a gallium nitride layer including an n-type region. The gallium nitride layer includes a first p-type well region and a second p-type well region that is provided on at least a portion of the first p-type well region and has a peak region with a higher p-type impurity concentration than the first p-type well region.

A semiconductor device structure comprising: a layer of compound semiconductor material; and a layer of polycrystalline CVD diamond material, wherein the layer of polycrystalline CVD diamond material is bonded to the layer of compound semiconductor material via a layer of nano-crystalline diamond which is directly bonded to the layer of compound semiconductor material, the layer of nano-crystalline diamond having a thickness in a range 5 to 50 nm and configured such that an effective thermal boundary resistance (TBR.sub.eff) as measured by transient thermoreflectance at an interface between the layer of compound semiconductor material and the layer of polycrystalline CVD diamond material is no more than 50 m.sup.2K/GW.

A method for effectively removing minute impurities of 1 μm or less in size that are present on a surface of an aluminum nitride single-crystal substrate without etching the surface includes scrubbing a surface of an aluminum nitride single-crystal substrate using a polymer compound material having lower hardness than an aluminum nitride single crystal, and an alkali aqueous solution having 0.01-1 mass % concentration of potassium hydroxide or sodium hydroxide, the alkali aqueous solution being absorbed in the polymer compound material.

A substrate includes: a support substrate having a first main surface and a surface layer region which includes at least the first main surface and is formed of any one material selected from the group consisting of boron nitride, molybdenum disulfide, tungsten disulfide, niobium disulfide, and aluminum nitride; and a graphene film disposed on the first main surface and having an atomic arrangement oriented in relation to an atomic arrangement of the material forming the surface layer region. Accordingly, the substrate is provided that enables a high mobility to be stably ensured in an electronic device manufactured to include the graphene film forming an electrically conductive portion.

There is provided an epitaxial substrate, including: a GaN substrate whose main surface is a c-plane; and a GaN layer epitaxially grown on the main surface, wherein the main surface includes a region where an off-angle is 0.4° or more, and an E3 trap concentration in the GaN layer grown on the region is 3.0×10.sup.13 cm.sup.−3 or less.