Method for the reuse of gallium nitride epitaxial substrates

Abstract

A method for the reuse of gallium nitride (GaN) epitaxial substrates uses band-gap-selective photoelectrochemical (PEC) etching to remove one or more epitaxial layers from bulk or free-standing GaN substrates without damaging the substrate, allowing the substrate to be reused for further growth of additional epitaxial layers. The method facilitates a significant cost reduction in device production by permitting the reuse of expensive bulk or free-standing GaN substrates.

Claims

1. A method for fabricating a device, comprising: providing a III-nitride substrate; growing one or more Indium Gallium Nitride (InGaN) sacrificial layers on or above the III-nitride substrate; growing one or more III-nitride device layers on or above the InGaN sacrificial layers; and selectively etching the InGaN sacrificial layers to separate the III-nitride device layers from the III-nitride substrate without substantially etching the III-nitride device layers or the III-nitride substrate, wherein the selectively etched InGaN sacrificial layers are crystal layers.

2. A device, comprising: a III-nitride substrate; one or more Indium Gallium Nitride (InGaN) sacrificial layers grown on or above the III-nitride substrate; and one or more III-nitride device layers grown on or above the InGaN sacrificial layers; wherein the InGaN sacrificial layers are selectively etched layers used to separate the III-nitride device layers from the III-nitride substrate without the III-nitride device layers or the III-nitride substrate being substantially etched, and the selectively etched layers are crystal layers.

3. The device of claim 2, wherein the device comprises an optoelectronic, electronic or thermoelectric device.

4. The device of claim 3, wherein the device comprises a light emitting diode, laser diode, photovoltaic cell or transistor.

5. The device of claim 2, wherein the III-nitride substrate is an epitaxy-ready bulk or free-standing III-nitride substrate.

6. The device of claim 2, wherein the III-nitride substrate is Gallium Nitride (GaN).

7. The device of claim 6, wherein the III-nitride substrate is polar, semipolar or nonpolar GaN.

8. The device of claim 2, wherein the III-nitride substrate is reusable after the III-nitride device layers are separated from the III-nitride substrate.

9. The device of claim 8, wherein the III-nitride substrate is processed after the III-nitride device layers are separated from the III-nitride substrate to prepare the III-nitride substrate for reuse.

10. The device of claim 2, wherein the III-nitride substrate has been previously used to grow a III-nitride device structure.

11. The device of claim 2, wherein the InGaN sacrificial layers are grown on an etched or etched and polished surface of the III-nitride substrate.

12. The device of claim 11, wherein the surface of the III-nitride substrate is epitaxy ready, with no difference in crystal quality, doping, and surface roughness as compared to a new epitaxy-ready III-nitride substrate.

13. The device of claim 11, wherein the surface of the III-nitride substrate has a surface roughness smoother than 1 nanometer (nm) root mean square (RMS) on an area of at least 10×10 micrometers.

14. The device of claim 2, wherein the InGaN sacrificial layers are selectively etched layers used to separate the III-nitride device layers from the III-nitride substrate without the III-nitride device layers or the III-nitride substrate being damaged, such that performance of the III-nitride device layers is not degraded and the III-nitride substrate can be reused.

15. The device of claim 14, wherein the performance of the III-nitride device layers is not degraded after the III-nitride device layers are separated from the III-nitride substrate as compared to III-nitride device layers grown on a new or unused III-nitride substrate.

16. The device of claim 2, wherein the InGaN sacrificial layers are selectively etched laterally and are completely removed, thereby freeing the III-nitride substrate from the III-nitride device layers.

17. The device of claim 2, wherein the InGaN sacrificial layers are exposed before being selectively etched.

18. The device of claim 2, further comprising one or more epitaxial layers grown on or above the III-nitride substrate, wherein the InGaN sacrificial layers are grown on or above the epitaxial layers.

19. The device of claim 18, wherein a contact is made to the epitaxial layers grown underneath the InGaN sacrificial layers in order to aid in extraction of carriers during band-gap-selective photoelectrochemical etching.

20. The device of claim 2, wherein the III-nitride device layers are sub-mounted to a carrier substrate.

21. A device, comprising: a III-nitride substrate; one or more Indium Gallium Nitride (InGaN) sacrificial layers grown on or above the III-nitride substrate; and one or more III-nitride device layers grown on or above the InGaN sacrificial layers; wherein the III-nitride substrate is separated from the III-nitride device layers after the InGaN sacrificial layers are selectively etched, and the selectively etched InGaN sacrificial layers are crystal layers.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Referring now to the drawings in which like reference numbers represent corresponding parts throughout:

(2) FIGS. 1(a) and 1(b) are a pair of scanning electron microscope (SEM) images showing epitaxial device layers after removal from a bulk GaN substrate, leaving the GaN substrate intact.

(3) FIGS. 2(a), 2(b), 2(c) and 2(d) together illustrate an exemplary process flow for substrate removal using PEC etching.

(4) FIG. 3 illustrates a method of fabricating a device.

(5) FIG. 4(a) illustrates a Vertical Cavity Surface Emitting Laser (VCSEL) device structure.

(6) FIG. 4(b) shows a scanning electron microscope (SEM) image of three completed VCSEL devices.

(7) FIG. 4(c) shows the near-field pattern of a 10-μm-diameter device operating above threshold.

(8) FIG. 4(d) illustrates light vs. current (L-I) curve for a nonpolar m-plane GaN VCSEL lasing under pulsed operation at 0.03% duty cycle.

(9) FIG. 4(e) illustrates optical emission spectrum of a nonpolar m-plane GaN VCSEL lasing under pulsed operation at 0.3% duty cycle.

(10) FIG. 4(f)-(g) illustrate a normalized light intensity vs. polarizer angle at various currents above and below threshold for the device shown in FIG. 4(a).

DETAILED DESCRIPTION OF THE INVENTION

(11) In the following description of the preferred embodiment, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration a specific embodiment in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention.

(12) Technical Description

(13) As noted above, substrates for the homoepitaxial growth of GaN, particularly bulk and non-c-plane substrates, are a significant portion of the cost of GaN devices, including Light Emitting Diodes (LEDs), laser diodes, transistors, and photovoltaic cells. While heteroepitaxy substrates such as sapphire can be removed using processes such as laser liftoff, no method exists for the removal and subsequent reuse of bulk or free-standing GaN substrates used for homoepitaxy of GaN. This is true for GaN substrates of polar, semipolar, and nonpolar orientations.

(14) The present invention uses band-gap-selective photoelectrochemical (PEC) etching to nondestructively remove bulk GaN substrates without damaging the substrate. Due to the bandgap-selective nature of Photoelectrochemical (PEC) etching, it is possible to selectively etch epitaxially-grown sacrificial layers, thereby removing devices from the growth substrate without damaging the devices or the substrate [8]. Such a process leaves the entire substrate intact. With an appropriate chemical-mechanical planarization process, the removed substrate could be reused again for further epitaxial growth and processing of devices. Since the substrate itself represents a significant portion of the cost of devices grown on bulk GaN, the ability to reuse substrates multiple times could yield substantial cost reductions on a per-device basis.

(15) The removal of a bulk GaN substrate from individual electronic and optoelectronic devices using photoelectrochemical etching of a sacrificial layer) has been demonstrated, showing this process to be feasible.

(16) FIGS. 1(a) and 1(b) are a pair of scanning electron microscope (SEM) images showing epitaxial device layers after removal from a bulk GaN substrate, leaving the GaN substrate intact. Specifically, FIG. 1(a) shows epitaxially-grown layers 100 bonded 102 to a submount 104 after substrate removal using PEC etching. FIG. 1(b) shows a bulk GaN substrate 106, which is intact with metal contacts, after substrate removal using PEC etching.

(17) The application of this invention to a product can follow the process flow outlined in FIGS. 2(a), 2(b), 2(c) and 2(d), as one example of multiple possible applications. Specifically, FIGS. 2(a), 2(b), 2(c) and 2(d) together illustrate an exemplary process flow for substrate removal using PEC etching.

(18) FIG. 2(a) shows epitaxial growth of an epitaxial layer 200, a sacrificial layer 202 (e.g., In.sub.xGa.sub.1-xN where 0<x≦1), and one or more device layers 204, on a bulk GaN substrate 206.

(19) FIG. 2(b) shows device processing including a vertical etch to expose the sacrificial layer 202.

(20) FIG. 2(c) shows wafer bonding the device layers 204 to carrier wafer or submount 208.

(21) FIG. 2(d) shows substrate removal through PEC etching. These steps are described in more detail below.

(22) An epitaxy-ready bulk GaN substrate, of any orientation, is produced internally or purchased from a commercial vendor. Epitaxial films including device layers 204 are grown on this substrate 206 to form electronic, optoelectronic or thermoelectric devices, such as LEDs, laser diodes, photovoltaic cells, transistors, or thermoelectric devices, as shown in FIG. 2(a). Before (or after) growing any number of the device layers 204, a sacrificial In.sub.xGa.sub.1-xN layer 202 is grown overlying the substrate 206. This sacrificial layer 202 could be comprised of one InGaN film of any thickness, or of multiple In.sub.xGa.sub.1-xN films (such as in the form of a superlattice). This sacrificial layer 202, placed underneath the device 204, can be selectively etched, without substantial etching of the surrounding GaN (including the GaN substrate 206), higher-band-gap InGaN, or AlGaN layers through the use of band-gap-selective PEC etching.

(23) After epitaxial growth, processing takes place according to the requirements for the desired device. Either as a part of the device fabrication or as a separate added step, a vertical dry or wet etch is performed to expose the sacrificial layer 202, as shown in FIG. 2(b). Additionally, a metal contact may be made to the n-type GaN grown underneath the sacrificial layer, which may aid in the extraction of carriers and may be a separate requirement from any contacts made to the devices themselves.

(24) The devices can then be bonded to a carrier substrate 208 using one of many possible methods for flip-chip bonding, such as Au—Au bonding or AuSn eutectic bonding, as shown in FIG. 2(c). The sample can then be submerged in any appropriate electrolyte solution (including, but not limited to, KOH, HCl, HNO.sub.3, etc.), and exposed to light that is above the bandgap of the In.sub.xGa.sub.1-xN sacrificial layer 202, but below the bandgap of GaN. The latter condition is a requirement that allows for etching of the In.sub.xGa.sub.1-xN sacrificial layer 202 while preventing undesirable etching of other surrounding layers, such as the GaN substrate 206. This light could come from any source, including narrow-emission sources like lasers or LEDs, or filtered broadband sources like a Xe lamp with a long-pass filter (using GaN itself as a filter will allow for any composition of In.sub.xGa.sub.1-xN to be etched while not allowing etching of GaN). The sacrificial In.sub.xGa.sub.1-xN layer 202 will etch laterally, and after some time will be completely removed (e.g., undercut), freeing the substrate 206 from the individual devices that were bonded to a carrier substrate 208, as shown in FIG. 2(d). The etch process may or may not include an applied bias or temperature control, which can assist in the etch process.

(25) After substrate removal, the devices including layers 204 (mounted on a carrier 208) can be further processed according to the desired device. The removed substrate 206 may still have metal contacts or raised mesa areas on the top surface, which are easily removed with acid etches that do not damage the substrate or other simple processing steps. There may also be previously-grown epitaxial films on the top surface. The etch process used to expose the sidewall of the sacrificial layer can also leave some features on the surface, generally very small in height (and this height can easily be controlled by controlling the depth of the top-down etch process). These epitaxial layers can then be removed by polishing, chemical-mechanical planarization (CMP), or other processes, and the surface can be treated to prepare it for further epitaxial growth. In general, the substrate may be prepared for reuse following the etch by planarization techniques, such as etching, lapping, polishing, etc., and/or by regrowth techniques, such as metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), etc.

(26) Through this process, a bulk GaN substrate can be returned to its original, epitaxy-ready state after every use. As such, a substrate can be used multiple times, allowing for a significant cost savings with every subsequent reuse. The limit on the number of reuse events for the substrate will be determined by the portion of the substrate thickness that must be removed to prepare the substrate for reuse. At some point, the substrate may become too thin for practical reuse. The monetary amount saved with each reuse will equal the difference between a new bulk GaN substrate from a commercial vendor and the cost of additional processing required for substrate reuse. These additional processing steps (and their cost) will vary according to the devices being fabricated. For instance, an additional metal deposition and patterning step may be necessary, or this step may be incorporated into another step required for device fabrication.

(27) Additional steps that may always be required are the polishing and surface preparation of the used substrate. Polishing and surface preparation is also required of any new substrate as well, so it is merely the degree of surface preparation required that will vary between new and reused substrates.

(28) Process Steps

(29) FIG. 3 illustrates a method of fabricating a device.

(30) Block 300 represents obtaining or preparing a used III-nitride substrate (e.g., a GaN substrate). The step can comprise performing an etch to remove one or more epitaxial layers from a bulk or free-standing GaN or III-nitride substrate, without damaging the substrate, thereby allowing the substrate to be reused for further growth of additional epitaxial layers. The etch can be a wet etch or a band-gap-selective PEC etch, for example.

(31) The etch can be performed on a sacrificial etch layer between the epitaxial layers and the substrate.

(32) The substrate can be a polar, semipolar or nonpolar orientation of GaN.

(33) The epitaxial layers can be sub-mounted to a carrier substrate before the etch is performed.

(34) The substrate can be an intact and reusable substrate following the etch. For example, the etched surface can have a surface roughness smoother than 1 nanometer (nm) root mean square (e.g., on a 10 micrometer×10 area as measured by Atomic Force Microscopy). The roughness can be uniform over the entire wafer (e.g., 2 inch wafer).

(35) In one or more embodiments, the surface of the used substrate after preparation is epitaxy ready, with no difference in crystal quality, doping, and surface roughness, etc., as compared to a new epitaxy ready substrate. For example, after PEC etching to remove the devices and then processing the substrate to make it epi-ready (lap/polish, CMP, chemical treatments, etc.), the reusable substrate can be the same as a new one.

(36) However, the substrate can be further prepared for reuse following the etch by planarization techniques, such as etching, lapping, polishing, etc. The substrate can be prepared for reuse following the etch by regrowth techniques, such as metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), etc. The preparation or regrowth can include growth of additional epitaxial layer(s) 200 (see FIGS. 2(a)-2(d)). The additional epitaxial layers (e.g., GaN) can be grown on the substrate following the etch.

(37) Block 302 represents growing an epitaxial film comprising a III-nitride optoelectronic or electronic device structure, on or above, or overlying, the used III-nitride substrate. The epitaxial film can be grown on an etched surface or etched and polished surface of the substrate, for example. The epitaxial film can comprise a III-nitride active region (e.g. InGaN) between a p-type III-nitride layer or region (e.g., GaN) and an n-type III-nitride (e.g., GaN) layer or region.

(38) The epitaxial film can be grown on or above a sacrificial layer grown on or above the substrate, for example.

(39) Block 304 represents the end result, a substrate or device or device structure (e.g., III-nitride film comprising an optoelectronic (e.g., LED, laser diode), electronic (e.g., transistor), solar cell, or thermoelectric device/device structure). The device can comprise a III-nitride epitaxial film grown on or above or overlying a used III-nitride substrate. For example, the substrate 206 in FIG. 2(a) can be a used substrate (in which case the device layers 202 comprise an epitaxial film grown on or above a used substrate).

(40) In one or more embodiments, the substrate 206 can have been used to grow at least 20 devices and/or the device's performance is not degraded as compared to a device grown on a new or non-used III-nitride substrate 206.

Example: Vertical Cavity Surface Emitting Laser (VCSEL)

(41) FIG. 4(a) shows a schematic illustration of the VCSEL device structure. The epitaxial structure was grown on a free-standing m-plane GaN substrate (nominally offcut by 1° in the −c-direction) using atmospheric-pressure metal-organic chemical vapor deposition. The active region is aligned with a peak of the optical standing wave and consists of 5 In.sub.0.10Ga.sub.0.90N (7 nm) quantum wells with GaN (5 nm) barriers and a 15 nm Mg-doped Al.sub.0.20Ga.sub.0.80N electron blocking layer. An additional region of 3 In.sub.0.12Ga.sub.0.88N (7 nm) quantum wells with GaN (5 nm) barriers was embedded in the n-GaN beneath the active region (sacrificial layer). This region was laterally undercut using band-gap-selective PEC etching after flip-chipping to separate the substrate from the devices. The placement of a 15 nm Al.sub.0.30Ga.sub.0.70N hole-blocking layer 50 nm above the sacrificial region served to define the cavity length (7.5λ) and to prevent hole transport to the device sidewalls during the lateral undercut PEC etch [9]. A mesa was defined by etching through the active region (stopping above the sacrificial region) and a SiN.sub.x dielectric was patterned for protection of the active region sidewalls during PEC etching and to define a current aperture, which ranges in diameter from 7 to 10 μm. Approximately 50 nm (λ/4-wave) of ITO was deposited via electron cyclotron resonance sputtering (using an AFTEX-7600 ECR Plasma Deposition System by MES AFTY Corporation) and patterned as a p-type ohmic intra-cavity contact and current spreading layer. A metal ring contact was formed around the current aperture before deposition of a λ/8-wave Ta.sub.2O.sub.5 interlayer to align the high-absorption ITO with the node of the optical standing wave and a 13-period SiO.sub.2/Ta.sub.2O.sub.5 distributed Bragg reflector (DBR). A second mesa etch was performed to expose the sidewalls of the sacrificial undercut layer and metal was patterned to form a bonding pad and to electrically connect the metal ring contact to the submount. The sample was then bonded to a gold-coated sapphire submount and the sacrificial In.sub.0.12Ga.sub.0.88N QWs were laterally etched by bandgap-selective PEC etching, using KOH and a 405 nm laser light source, until the substrate was removed. Ohmic ring n-contacts were formed on the bonded mesas in alignment with the current apertures and a top-down bandgap-selective PEC etch was performed, with the Al.sub.0.30Ga.sub.0.70N acting as a highly-selective stop-etch layer. Finally, a 10-period SiO.sub.2/Ta.sub.2O.sub.2 DBR was deposited.

(42) As indicated above, the epitaxial structure includes a lower-bandgap sacrificial region underneath the device at a well-defined location, such that the location of the In.sub.xGa.sub.1-xN layer would define the length of the vertical cavity to be ideally suited for the desired VCSEL device.

(43) This lower-bandgap material would typically be In.sub.xGa.sub.1-xN of variable compositions, such that it could be selectively etched by a suitable light source, such as a filtered broadband source or a narrow-emission light source.

(44) The Indium (In) containing layer should be preferred for the lower-bandgap sacrificial layer because it is easier to etch out the sacrificial layer by etching. This sacrificial region could be a single layer or a set of several layers, of any thickness. In addition, this selective etching is more preferred for nonpolar or semipolar VCSEL because the quantum-confined Stark effect (QCSE) limits the thickness of sacrificial layers that can be used with polar/c-plane sacrificial layers. In polar/c-plane devices, the built-in electric field that is perpendicular to the sacrificial layer separates the electrons and holes to opposite sides of the layer. Since it is holes that participate in PEC etching, this causes non-uniform etching in polar/c-plane sacrificial layers, so layer thicknesses must be kept very thin to compensate. Thus, superlattices must be used and the etching rate may suffer due to the thin sacrificial layers used: lower surface area and increased aspect ratio during lateral etching can both limit etching rate. Nonpolar and semipolar planes limit the QCSE in the sacrificial layers (remove it completely in the case of nonpolar), and thereby remove the design restrictions placed on the sacrificial layer by QCSE in the polar/c-plane devices.

(45) FIG. 4(b) shows a scanning electron microscope (SEM) image of three completed VCSEL devices. FIG. 4(c) shows the near-field pattern of a 10-μm-diameter VCSEL device operating above threshold. FIG. 4(d) illustrates light vs. current (L-I) curve for a nonpolar m-plane GaN VCSEL lasing under pulsed operation at 0.03% duty cycle. FIG. 4(e) illustrates optical emission spectrum of a nonpolar m-plane GaN VCSEL lasing under pulsed operation at 0.3% duty cycle. FIGS. 4(f) and (g) illustrates a normalized light intensity vs. polarizer angle at various currents above and below threshold for the device shown in FIG. 4(a).

(46) Further information on fabrication of the VCSEL can be found in [10] and U.S. Provisional Patent Application Ser. No. 61/673,966, filed on Jul. 20, 2012, by Casey Holder, Daniel F. Feezell, Steven P. DenBaars, and Shuji Nakamura, entitled “STRUCTURE AND METHOD FOR THE FABRICATION OF A GALLIUM NITRIDE VERTICAL CAVITY SURFACE EMITTING LASER”, which application is incorporated by reference herein.

(47) Benefits and Advantages

(48) Bulk or free-standing GaN substrates (including polar, semipolar, and nonpolar orientations) offer significant performance advantages for electronic and optoelectronic devices over conventional heteroepitaxy substrates, such as sapphire or silicon carbide, due to the resulting reduction in threading dislocation densities. However, bulk GaN substrates represent a significant cost increase over conventional heteroepitaxy substrates. This invention will allow for the reuse of bulk GaN substrates, thereby reducing the per-device cost of optoelectronic or electronic devices grown on bulk or free-standing GaN substrates.

(49) One or more embodiments of the invention obtain high-performance electronic and optoelectronic devices produced at a lower cost through the reuse of bulk or free-standing GaN substrates, with no degradation of the device performance caused by the reuse of the substrate.

(50) For example, one or more embodiments of the invention can be used to significantly reduce the cost of flip-chip bonded electronic, optoelectronic or thermoelectric devices (such as LEDs, laser diodes, photovoltaic cells, transistors, and Photoelectrochemical (PEC) cells for gas generation) grown homoepitaxially on reusable bulk or free-standing GaN substrates. This cost savings would be realized through the option of reusing expensive bulk or free-standing GaN substrates of any orientation (c-plane, non-polar, or semi-polar).

(51) Free-standing bulk GaN substrates used for the growth and fabrication of a variety of optoelectronic or electronic devices can be removed and reused for future growths of similar devices with no degradation in the quality of the substrates or the devices grown on them.

(52) Possible Modifications

(53) The present invention has experimentally demonstrated the bonding of individual (In,Al,Ga)N devices to a submount, and has demonstrated the removal of a free-standing GaN epitaxial substrate through band-gap-selective (PEC) etching of a sacrificial layer. However, other methods of removing or etching the substrate are possible.

(54) The present invention has demonstrated the reuse of a bulk GaN substrate (after bonding and removal of individual devices) for subsequent epitaxial growth, as well as device production. However, other reuse of other substrates or other III-nitride substrates is also included.

(55) Nomenclature

(56) The terms “(AlInGaN)” “(In,Al)GaN”, or “GaN” as used herein (as well as the terms “III-nitride,” “Group-III nitride”, or “nitride,” used generally) refer to any alloy composition of the (Ga,Al,In,B)N semiconductors having the formula Ga.sub.wAl.sub.xAn.sub.yB.sub.zN where 0≦w≦1, 0≦x≦1, 0≦y≦1, 0≦z≦1, and w+x+y+z=1. These terms are intended to be broadly construed to include respective nitrides of the single species, Ga, Al, In and B, as well as binary, ternary and quaternary compositions of such Group III metal species. Accordingly, it will be appreciated that the discussion of the invention hereinafter in reference to GaN and InGaN materials is applicable to the formation of various other (Ga,Al,In,B)N material species. Further, (Ga,Al,In,B)N materials within the scope of the invention may further include minor quantities of dopants and/or other impurity or inclusional materials.

(57) One approach to decreasing polarization effects in III-nitride devices is to grow the devices on a nonpolar substrate or nonpolar planes of the crystal. These include the {11-20} planes, known collectively as a-planes, and the {10-10} planes, known collectively as m-planes. Such planes contain equal numbers of gallium and nitrogen atoms per plane and are charge-neutral. Subsequent nonpolar layers are equivalent to one another, so the bulk crystal will not be polarized along the growth direction.

(58) Another approach to reducing polarization effects in III-nitride devices is to grow the devices on a semipolar substrate or semipolar planes of the crystal. The term “semipolar plane” can be used to refer to any plane that cannot be classified as c-plane, a-plane, or m-plane. In crystallographic terms, a semipolar plane would be any plane that has at least two nonzero h, i, or k Miller indices and a nonzero l Miller index. Subsequent semipolar layers are equivalent to one another, so the bulk crystal will have reduced polarization along the growth direction.

REFERENCES

(59) The following references are incorporated by reference herein: [1] R. Dwiliński et al., “Bulk ammonothermal GaN,” Journal of Crystal Growth, vol. 311, no. 10, pp. 3015-3018, May 2009. [2] K. M. Kelchner et al., “Nonpolar AlGaN-Cladding-Free Blue Laser Diodes with InGaN Waveguiding,” Applied Physics Express, vol. 2, no. 7, p. -, 2009. [3] A. Tyagi et al., “AlGaN-Cladding Free Green Semipolar GaN Based Laser Diode with a Lasing Wavelength of 506.4 nm,” Applied Physics Express, vol. 3, no. 1, p. 011002, January 2010. [4] J. W. Raring et al., “High-Efficiency Blue and True-Green-Emitting Laser Diodes Based on Non-c-Plane Oriented GaN Substrates,” Applied Physics Express, vol. 3, no. 11, pp. 112101-112101, 2010. [5] K. Fujito, S. Kubo, H. Nagaoka, T. Mochizuki, H. Namita, and S. Nagao, “Bulk GaN crystals grown by HVPE,” Journal of Crystal Growth, vol. 311, no. 10, pp. 3011-3014, May 2009. [6] O. B. Shchekin et al., “High performance thin-film flip-chip InGaN—GaN light-emitting diodes,” Applied Physics Letters, vol. 89, no. 7, p. 071109, 2006. [7] J. J. Xu et al., “1-8-GHz GaN-based power amplifier using flip-chip bonding,” Microwave and Guided Wave Letters, IEEE, vol. 9, no. 7, pp. 277-279, 1999. [8] A. C. Tamboli, M. C. Schmidt, A. Hirai, S. P. DenBaars, and E. L. Hu, “Photoelectrochemical Undercut Etching of m-Plane GaN for Microdisk Applications,” Journal of The Electrochemical Society, vol. 156, no. 10, p. H767, 2009. [9] A. Tamboli, M. Schmidt, S. Rajan, J. Speck, U. Mishra, S. DenBaars, and E. Hu: J. Elecrochem. Soc. 156 (2009) H47. [10] C. Holder et. al., “Demonstration of Nonpolar GaN-based Vertical Cavity Surface Emitting Lasers,” Appl. Phys. Express 5 (2012) 092104.

(60) Conclusion

(61) This concludes the description of the preferred embodiment of the present invention. The foregoing description of one or more embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.