A method of performing heteroepitaxy comprises exposing an OP-GaAs template in an HVPE reactor to a carrier gas, a first precursor gas, a second precursor gas (2pg), a Group II element, and a third precursor gas (3pg), to form an epitaxial growth of one of GaAs, GaP, and GaAsP directly on the OP-GaAs template; wherein the carrier gas is H.sub.2, wherein the first precursor is HCl, the Group II element is Ga; and wherein the second (V or VI group) precursor is one or more of AsH.sub.3 (arsine) and PH.sub.3 (phosphine), and the third precursor is one or more of PH.sub.3 and AsH.sub.3. For an epitaxial growth of GaAsP, the method may further comprise flowing the second and third precursors through the HVPE reactor at a 2pg:3pg ratio of about 1:0; heating the OP-template to 500° C.-900° C.; and gradually changing the 2pg:3pg ratio toward 0:1 over time.

A method of performing heteroepitaxy comprises exposing a substrate to a carrier gas, a first precursor gas, a Group II/III element, and a second precursor gas, to form a heteroepitaxial growth of one of GaAs, AlAs, InAs, GaP, InP, ZnSe, GaSe, CdSe, InSe, ZnTe, CdTe, GaTe, HgTe, GaSb, InSb, AlSb, CdS, GaN, and AlN on the substrate; wherein the substrate comprises one of GaAs, AlAs, InAs, GaP, InP, ZnSe, GaSe, CdSe, InSe, ZnTe, CdTe, GaTe, HgTe, GaSb, InSb, AlSb, CdS, GaN, and AlN; wherein the carrier gas is H.sub.2, wherein the first precursor is HCl, the Group II/III element comprises at least one of Zn, Cd, Hg, Al, Ga, and In; and wherein the second precursor is one of AsH.sub.3 (arsine), PH.sub.3 (phosphine), H.sub.2Se (hydrogen selenide), H.sub.2Te (hydrogen telluride), SbH.sub.3 (hydrogen antimonide), H.sub.2S (hydrogen sulfide), and NH.sub.3 (ammonia). The process may be an HVPE (hydride vapor phase epitaxy) process.

A method for depositing III-V alloys on substrates and compositions therefrom. A first layer comprises a Group III element. A second layer comprises a silica. A substrate has a surface. The second layer is deposited onto a first layer. The depositing is performed by a sol-gel method. The second layer is exposed to a precursor that comprises a Group V element. At least one of the precursor or the Group V element diffuse through the silica. The first layer is transformed into a solid layer comprising a III-V alloy, wherein at least a portion of the first layer to a liquid. The silica retains the liquified first layer, enabling at least one of the precursor or the Group V element to diffuse into the liquid, resulting in the forming of the III-V alloy.

Provided is an indium phosphide substrate, a method for manufacturing indium phosphide substrate, and a semiconductor epitaxial wafer capable of suppressing an occurrence of contamination of the surface of the indium phosphide substrate caused by residues at the edge part. An indium phosphide substrate, wherein a surface roughness of an edge part of the substrate has a root mean square height Sq of 0.15 μm or less, as measured by a laser microscopy on the entire surface of the edge part.

A method of producing graphene or other two-dimensional material such as graphene including heating the substrate held within a reaction chamber to a temperature that is within a decomposition range of a precursor, and that allows two-dimensional crystalline material formation from a species released from the decomposed precursor; establishing a steep temperature gradient (preferably >1000° C. per meter) that extends away from the substrate surface towards an inlet for the precursor; and introducing precursor through the relatively cool inlet and across the temperature gradient towards the substrate surface. The steep temperature gradient ensures that the precursor remains substantially cool until it is proximate the substrate surface thus minimizing decomposition or other reaction of the precursor before it is proximate the substrate surface. The separation between the precursor inlet and the substrate is less than 100 mm.

Methods for fabricating vertical cavity surface emitting lasers (VCSELs) on a large wafer are provided. An un-patterned epi layer form is bonded onto a first reflector form. The first reflector form includes a first reflector layer and a wafer of a first substrate type. The un-patterned epi layer form includes a plurality of un-patterned layers on a wafer of a second substrate type. The first and second substrate types have different thermal expansion coefficients. A resulting bonded blank is substantially non-varying in a plane that is normal to an intended emission direction of the VCSEL. A first regrowth is performed to form first regrowth layers, some of which are patterned to form a tunnel junction pattern. A second regrowth is performed to form second regrowth layers. A second reflector form is bonded onto the second regrowth layers, wherein the second reflector form includes a second reflector layer.

A semiconductor laminate includes a substrate composed of InP, a first buffer layer composed of InP containing less than 1×10.sup.21 cm.sup.−3 Sb and disposed on the substrate, and a second buffer layer composed of InGaAs and disposed on the first buffer layer. The first buffer layer includes a first layer that has a higher concentration of Sb than the substrate and that is arranged to include a first main surface which is a main surface of the first buffer layer on the substrate side. The second buffer layer includes a second layer that has a lower concentration of Sb than the first layer and that is arranged to include a second main surface which is a main surface of the second buffer layer on the first buffer layer side.

First, in a first step S101, a semiconductor layer composed of a p type Group III-V compound semiconductor is prepared. The semiconductor layer may be composed of a Group III-V compound semiconductor crystal. Next, in a second step S102, gold is grown on a surface of the above semiconductor layer according to an electroless plating method to form fine gold particles. In this step, for example, an electroless plating solution of gold is brought into contact with a surface of the semiconductor layer such as by immersing the semiconductor layer in the electroless gold plating solution. In addition, in this plating treatment, the liquid temperature of the electroless gold plating solution may be room temperature (about 20° C. to 30° C.).

A method is presented for fabricating a substrate comprised of a compound semiconductor. The method includes: growing a sacrificial layer onto a parent substrate; growing an epitaxial template layer on the sacrificial layer; removing the template layer from the parent substrate using an epitaxial lift-off procedure; and bonding the removed template layer to a host substrate using Van der Waals forces and thereby forming a compound semiconductor substrate.

Disclosed is a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device comprises a first III-V compound semiconductor layer having a first material structure, a second semiconductor layer having a second material structure and a third semiconductor layer having a third material structure. An interface between the first semiconductor layer and the second semiconductor layer consists of at least one corresponding crystalline terminating oxide layer of the first semiconductor layer, and an interface between the second semiconductor layer and the third semiconductor layer comprises at least one corresponding crystalline terminating oxide layer of a III-V compound semiconductor layer.