Disclosed is a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device comprises a first III-V compound semiconductor layer having a first material structure, a second semiconductor layer having a second material structure and a third semiconductor layer having a third material structure. An interface between the first semiconductor layer and the second semiconductor layer consists of at least one corresponding crystalline terminating oxide layer of the first semiconductor layer, and an interface between the second semiconductor layer and the third semiconductor layer comprises at least one corresponding crystalline terminating oxide layer of a III-V compound semiconductor layer.

To prevent the surface of a base substrate and the bottom surface of a separated semiconductor epitaxial layer from being bonded to each other even after a removal layer is removed, the semiconductor substrate includes a base substrate, a first removal layer provided on the base substrate, a second removal layer provided above the first removal layer, and a semiconductor epitaxial layer provided above the second removal layer, and an etching rate of the second removal layer for a predetermined etching material is larger than the etching rate of the first removal layer for the predetermined etching material.

What is provided here are: a step of forming a first semiconductor layer on a base member; a step of forming a mask on the first semiconductor layer; a step of etching the first semiconductor layer by using the mask, to thereby form a semiconductor structure; a step of forming a second semiconductor layer in a region abutting on a side surface of the semiconductor structure, said second semiconductor layer having a convex portion abutting to the mask; a convex-portion removing step of removing the convex portion by supplying an etching gas thereto; and a regrown-layer forming step of supplying a material gas onto the semiconductor structure and the second semiconductor layer, to thereby form a regrown layer; wherein the convex-portion removing step and the regrown-layer forming step are executed in a same manufacturing apparatus.

A method of producing graphene or other two-dimensional material such as graphene including heating the substrate held within a reaction chamber to a temperature that is within a decomposition range of a precursor, and that allows two-dimensional crystalline material formation from a species released from the decomposed precursor; establishing a steep temperature gradient (preferably >1000° C. per meter) that extends away from the substrate surface towards an inlet for the precursor; and introducing precursor through the relatively cool inlet and across the temperature gradient towards the substrate surface. The steep temperature gradient ensures that the precursor remains substantially cool until it is proximate the substrate surface thus minimizing decomposition or other reaction of the precursor before it is proximate the substrate surface. The separation between the precursor inlet and the substrate is less than 100 mm.

The present disclosure provides a method for preparing heterostructure, which includes providing a donor substrate and forming a sacrificial layer on a surface of the donor substrate; forming a thin film cover layer on a surface of the sacrificial layer, wherein a top surface of the thin film cover layer is an implantation surface; performing ion implantation from the implantation surface, such that a defect layer is formed in the sacrificial layer; providing an acceptor substrate, and bonding the acceptor substrate to the implantation surface of the thin film cover layer; removing the sacrificial layer along the defect layer. The method for preparing the heterostructure of the present disclosure can successfully transfer the thin film cover layer to the acceptor substrate. The present disclosure can provide a compliant substrate, while the semiconductor donor substrate material can be reused, therefore is energy-efficient and environmental-friendly.

Provided is a semiconductor device including graphene. The semiconductor device includes: a substrate including an insulator and a semiconductor; and a graphene layer configured to directly grow only on a surface of the semiconductor, wherein the semiconductor includes at least one of a group IV material and a group III-V compound.

A device includes: (1) a boron arsenide substrate; and (2) an integrated circuit disposed in or over the boron arsenide substrate.

A nanowire structure includes a substrate, a graded planar buffer layer, a patterned mask, and a nanowire. The graded planar buffer layer is on the substrate. The patterned mask is on the graded planar buffer layer and includes an opening through which the graded planar buffer layer is exposed. The nanowire is on the graded planar buffer layer in the opening of the patterned mask. A lattice constant of the graded planar buffer layer is between a lattice constant of the substrate and a lattice constant of the nanowire. By providing the graded planar buffer layer, lattice mismatch between the nanowire and the substrate can be reduced or eliminated, thereby improving the quality and performance of the nanowire structure.

A method of manufacturing a semiconductor device includes forming a first epitaxial layer on a first substrate. The first substrate includes a first semiconductor material having a first lattice constant and the first epitaxial layer includes a second semiconductor material having a second lattice constant different from the first lattice constant. The method also includes disposing a graphene layer on the first epitaxial layer and forming a second epitaxial layer comprising the second semiconductor material on the graphene layer. This method can increase the substrate reusability, increase the release rate of functional layers, and realize precise control of release thickness.

Provided is a semiconductor epitaxial structure including a nucleation layer disposed on a substrate; a buffer layer disposed on the nucleation layer; a semiconductor layer disposed on the buffer layer; a barrier layer disposed on the semiconductor layer; and a cap layer disposed on the barrier layer. In a case where a bowing of the semiconductor epitaxial structure is less than or equal to +/30 m, a maximum value or a minimum value of a ratio of a thickness of the buffer layer to a thickness of the semiconductor layer is represented as following formula: Y=aX1bX2+cX3, X10 nm, X2750 nm, X3515 nm, wherein X1 is a thickness of the nucleation layer, X2 is the thickness of the buffer layer, X3 is the thickness of the semiconductor layer, a, b and c are constants respectively, and Y is a ratio of X3 to X2.