A semiconductor device includes a substrate, a P-well region, a first N-type metal oxide semiconductor (NMOS) transistor provided in the P-well region, a second NMOS transistor provided on the substrate, and a common body bias region provided between the first NMOS transistor and the second NMOS transistor and contacting both the P-well region and the substrate.

A nanowire device includes a first component formed on a substrate and a second component disposed apart from the first component on the substrate. A nanowire is configured to connect the first component to the second component. An anchor pad is formed along a span of the nanowire and configured to support the nanowire along the span to prevent sagging.

An encapsulated substrate includes a zinc oxide substrate and a composite barrier layer. The composite barrier layer includes a first film layer having a first material different from zinc oxide, a second film layer covered on a surface of the first film layer and having a second material different from the zinc oxide and the first material, and an active layer formed on the composite barrier layer and corresponding to an acting surface of a zinc oxide substrate and having an acting material different from the zinc oxide.

A semiconductor device is manufactured using a transistor in which an oxide semiconductor is included in a channel region and variation in electric characteristics due to a short-channel effect is less likely to be caused. The semiconductor device includes an oxide semiconductor film having a pair of oxynitride semiconductor regions including nitrogen and an oxide semiconductor region sandwiched between the pair of oxynitride semiconductor regions, a gate insulating film, and a gate electrode provided over the oxide semiconductor region with the gate insulating film positioned therebetween. Here, the pair of oxynitride semiconductor regions serves as a source region and a drain region of the transistor, and the oxide semiconductor region serves as the channel region of the transistor.

In a method of treating a semiconductor substrate, a plurality of active regions and a plurality of trench isolation regions are formed by selectively etching the semiconductor substrate. The semiconductor substrate is washed by providing deionized water to the semiconductor substrate. A silicon-based solution is provided to the semiconductor substrate by replacing the deionized water disposed on the semiconductor substrate with the silicon-based solution. A silicon oxide material is formed from the silicon-based solution by performing a heat treatment on the silicon-based solution and the semiconductor substrate. The silicon oxide material fills the trench isolation regions.

An encapsulated substrate includes a zinc oxide substrate and a composite barrier layer. The composite barrier layer includes a first film layer having a first material different from zinc oxide, a second film layer covered on a surface of the first film layer and having a second material different from the zinc oxide and the first material, and an active layer formed on the composite barrier layer and corresponding to an acting surface of a zinc oxide substrate and having an acting material different from the zinc oxide.

A semiconductor device is manufactured using a transistor in which an oxide semiconductor is included in a channel region and variation in electric characteristics due to a short-channel effect is less likely to be caused. The semiconductor device includes an oxide semiconductor film having a pair of oxynitride semiconductor regions including nitrogen and an oxide semiconductor region sandwiched between the pair of oxynitride semiconductor regions, a gate insulating film, and a gate electrode provided over the oxide semiconductor region with the gate insulating film positioned therebetween. Here, the pair of oxynitride semiconductor regions serves as a source region and a drain region of the transistor, and the oxide semiconductor region serves as the channel region of the transistor.

A method is provided that includes forming a word line above a substrate, forming a bit line above the substrate, forming a nonvolatile memory material between the word line and the bit line, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line. The word line is disposed in a first direction, and includes a first word line portion and a second word line portion. The second word line portion of the word line includes a first conductive oxide material. The bit line is disposed in a second direction perpendicular to the first direction. The nonvolatile memory material includes a barrier oxide material layer and a second conductive oxide material layer, with the barrier oxide material layer disposed adjacent the second word line portion of the word line.

A method of producing graphene or other two-dimensional material such as graphene including heating the substrate held within a reaction chamber to a temperature that is within a decomposition range of a precursor, and that allows two-dimensional crystalline material formation from a species released from the decomposed precursor; establishing a steep temperature gradient (preferably >1000 C. per meter) that extends away from the substrate surface towards an inlet for the precursor; and introducing precursor through the relatively cool inlet and across the temperature gradient towards the substrate surface. The steep temperature gradient ensures that the precursor remains substantially cool until it is proximate the substrate surface thus minimizing decomposition or other reaction of the precursor before it is proximate the substrate surface. The separation between the precursor inlet and the substrate is less than 100 mm.

A high frequency device includes a first nitride semiconductor layer; a second nitride semiconductor layer provided on the first nitride semiconductor layer, and a third nitride semiconductor layer provided on the second nitride semiconductor layer. The second nitride semiconductor layer includes indium atoms, and has a layer thickness in a range of not less than 0.26 nanometers and not more than 100 nanometers.