Patent classifications
H01L21/02403
SUPPORT FOR LONG CHANNEL LENGTH NANOWIRE TRANSISTORS
A nanowire device includes a first component formed on a substrate and a second component disposed apart from the first component on the substrate. A nanowire is configured to connect the first component to the second component. An anchor pad is formed along a span of the nanowire and configured to support the nanowire along the span to prevent sagging.
METHOD OF FORMING A MEMORY DEVICE IN A RECESSED FEATURE
A method of forming a memory device on a substrate includes depositing a first electrode layer within a recessed feature of the substrate using a first atomic layer deposition process, and depositing an amorphous transition metal oxide layer over the first electrode layer using a second atomic layer deposition process at a first substrate temperature. And the method further includes, while maintaining an amorphous state of the amorphous transition metal oxide layer, depositing a second electrode layer over the amorphous transition metal oxide layer using a third atomic layer deposition process at a second substrate temperature, the second substrate temperature being lower than a recrystallization temperature of an amorphous transition metal oxide material of the amorphous transition metal oxide layer, and the first electrode layer, the amorphous transition metal oxide layer, and the second electrode layer forming a memory layer stack.
Gate-all-around integrated circuit structures having insulator substrate
Gate-all-around integrated circuit structures having an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator substrate, are described. For example, an integrated circuit structure includes a semiconductor fin on an insulator substrate. A vertical arrangement of horizontal nanowires is over the semiconductor fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal nanowires, and the gate stack is overlying a channel region of the semiconductor fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal nanowires and the semiconductor fin.
SEMICONDUCTOR DEVICE
A transistor includes a multilayer film in which an oxide semiconductor film and an oxide film are stacked, a gate electrode, and a gate insulating film. The multilayer film overlaps with the gate electrode with the gate insulating film interposed therebetween. The multilayer film has a shape having a first angle between a bottom surface of the oxide semiconductor film and a side surface of the oxide semiconductor film and a second angle between a bottom surface of the oxide film and a side surface of the oxide film. The first angle is acute and smaller than the second angle. Further, a semiconductor device including such a transistor is manufactured.
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING INSULATOR SUBSTRATE
Gate-all-around integrated circuit structures having an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator substrate, are described. For example, an integrated circuit structure includes a semiconductor fin on an insulator substrate. A vertical arrangement of horizontal nanowires is over the semiconductor fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal nanowires, and the gate stack is overlying a channel region of the semiconductor fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal nanowires and the semiconductor fin.