A layered structure comprising a substrate having a first deformation. Also one or more device layers forming a device and having a second deformation. A deformation control layer which is pseudomorphic with respect to the substrate and having a third deformation. The deformation control layer is selected such that a sum of the first, second and third deformations matches a target level of deformation. Advantageously the layered structure has a controlled, known deformation which can be compressive, tensile or zero.

An embodiment includes a III-V material based device, comprising: a first III-V material based buffer layer on a silicon substrate; a second III-V material based buffer layer on the first III-V material based buffer layer, the second III-V material including aluminum; and a III-V material based device channel layer on the second III-V material based buffer layer. Another embodiment includes the above subject matter and the first and second III-V material based buffer layers each have a lattice parameter equal to the III-V material based device channel layer. Other embodiments are included herein.

The present invention relates to a method of manufacturing semiconductor materials comprising interface layers of group III-V materials in combination with Si substrates. Especially the present invention is related to a method of manufacturing semiconductor materials comprising GaAs in combination with Si(111) substrates, wherein residual strain due to different thermal expansion coefficient of respective materials is counteracted by introducing added layer(s) compensating the residual strain.

A method for forming a material having a Perovskite single crystal structure includes alternately growing, on a substrate, each of a plurality of first layers and each of a plurality of second layers having compositions different from the plurality of first layers and forming a material having a Perovskite single crystal structure by annealing the plurality of first layers and the plurality of second layers.

Embodiments of the invention generally relate processes for epitaxial growing Group III/V materials at high growth rates, such as about 30 μm/hr or greater, for example, about 40 μm/hr, about 50 μm/hr, about 55 μm/hr, about 60 μm/hr, or greater. The deposited Group III/V materials or films may be utilized in solar, semiconductor, or other electronic device applications. In some embodiments, the Group III/V materials may be formed or grown on a sacrificial layer disposed on or over the support substrate during a vapor deposition process. Subsequently, the Group III/V materials may be removed from the support substrate during an epitaxial lift off (ELO) process. The Group III/V materials are thin films of epitaxially grown layers which contain gallium arsenide, gallium aluminum arsenide, gallium indium arsenide, gallium indium arsenide nitride, gallium aluminum indium phosphide, phosphides thereof, nitrides thereof, derivatives thereof, alloys thereof, or combinations thereof.

Semiconductor devices are provided which comprise III-V FINFET devices that are formed with different semiconductor fin widths to obtain different threshold voltages, as well as methods for fabricating such III-V FINFET devices. For example, a semiconductor device comprises first and second semiconductor fins, which are formed of a III-V compound semiconductor material, and which have a first width W1 and a second width W2, respectively, wherein W1 is less than W2. First and second gate structures of first and second FINFET devices are formed over a portion of the first and second semiconductor fins, respectively. The first FINFET device comprises a first threshold voltage and the second FINFET device comprises a second threshold voltage. The first threshold voltage is greater than the second threshold voltage as a result of the first width W1 being less than the second width W2.

Semiconductor devices including a subfin including a first III-V compound semiconductor and a channel including a second III-V compound semiconductor are described. In some embodiments the semiconductor devices include a substrate including a trench defined by at least two trench sidewalls, wherein the first III-V compound semiconductor is deposited on the substrate within the trench and the second III-V compound semiconductor is epitaxially grown on the first III-V compound semiconductor. In some embodiments, a conduction band offset between the first III-V compound semiconductor and the second III-V compound semiconductor is greater than or equal to about 0.3 electron volts. Methods of making such semiconductor devices and computing devices including such semiconductor devices are also described.

Methods and structures includes providing a substrate, forming a prelayer over a substrate, forming a barrier layer over the prelayer, and forming a channel layer over the barrier layer. Forming the prelayer may include growing the prelayer at a graded temperature. Forming the barrier layer is such that the barrier layer may include GaAs or InGaAs. Forming the channel layer is such that the channel layer may include InAs or an Sb-based heterostructure. Thereby structures are formed.

Provided is a semiconductor light-emitting element having improved light emission output. The semiconductor light-emitting element includes a light-emitting layer having a layered structure in which a first III-V compound semiconductor layer and a second III-V compound semiconductor layer having different composition ratios are repeatedly stacked. The first and second III-V compound semiconductor layers each contain three or more types of elements that are selected from Al, Ga, and In and from As, Sb, and P. The composition wavelength difference between the composition wavelength of the first III-V compound semiconductor layer and the composition wavelength of the second III-V compound semiconductor layer is 50 nm or less. The ratio of the lattice constant difference between the lattice constant of the first III-V compound semiconductor layer and the lattice constant of the second III-V compound semiconductor layer is not less than 0.05% and not more than 0.60%.

This invention is directed toward a method for manufacturing a semiconductor device with a heterostructure comprises covering a semiconductor structure with a seed layer structure; forming one or more separated circularly shaped openings in the seed layer structure to expose the semiconductor structure therein, and leave the seed layer structure outside the one or more separated circularly shaped openings; forming an insulator layer thereon; etching the obtained structure to (i) expose at least a portion of the seed layer structure, such that the exposed at least portion of the seed layer structure surrounds each of the one or more separated circularly shaped openings, and (ii) optionally expose the semiconductor structure, in the one or more separated circularly shaped openings; and epitaxially growing a semiconductor layer from the exposed at least portion of the seed layer structure, firstly mainly vertically and then into each of the one or more separated circularly shaped openings until the epitaxially grown semiconductor layer coalesces with the insulator layer or the semiconductor structure in each of the one or more separated circularly shaped openings.