H01L21/02472

GAS SENSOR AND METHOD OF MANUFACTURING THE SAME
20200003717 · 2020-01-02 ·

A gas sensor includes a substrate, a thin film metallic glass, an ultrananocrystalline diamond layer and a sensor structure. The thin film metallic glass is formed on the substrate. The ultrananocrystalline diamond layer partially covers the thin film metallic glass. The sensor structure includes a seed layer formed on the ultrananocrystalline diamond layer and a plurality of nanostructures formed on the seed layer.

ULTRAWIDE BANDGAP SEMICONDUCTOR DEVICES INCLUDING MAGNESIUM GERMANIUM OXIDES
20240096970 · 2024-03-21 · ·

Various forms of Mg.sub.xGe.sub.1-xO.sub.2-x are disclosed, where the Mg.sub.xGe.sub.1-xO.sub.2-x are epitaxial layers formed on a substrate comprising a substantially single crystal substrate material. The epitaxial layer of Mg.sub.xGe.sub.1-xO.sub.2-x has a crystal symmetry compatible with the substrate material. Semiconductor structures and devices comprising the epitaxial layer of Mg.sub.xGe.sub.1-xO.sub.2-x are disclosed, along with methods of making the epitaxial layers and semiconductor structures and devices. Also disclosed is single crystal Mg.sub.xGe.sub.1-xO.sub.2-x, with x having a value of 0?x<1. The single crystal Mg.sub.xGe.sub.1-xO.sub.2-x may comprise a dopant chosen from Ga, Al, Li.sup.+, N.sup.3+. The single crystal Mg.sub.xGe.sub.1-xO.sub.2-x may comprise a p-type conductivity.

SEED LAYER FOR FERROELECTRIC MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
20240087887 · 2024-03-14 ·

A method includes: forming a bottom electrode over a substrate; depositing a first seed layer over the bottom electrode, the first seed layer having an amorphous crystal phase; performing a first surface treatment on the first seed layer, wherein after the first surface treatment the first seed layer includes at least one of a tetragonal crystal phase and an orthorhombic crystal phase; depositing a dielectric layer over the bottom electrode adjacent to the first seed layer; depositing an upper layer over the dielectric layer; and performing a thermal operation on the dielectric layer to thereby convert the dielectric layer into a ferroelectric layer.

EPITAXIAL OXIDE MATERIALS, STRUCTURES, AND DEVICES
20240072205 · 2024-02-29 · ·

The present disclosure provides techniques for epitaxial oxide materials, structures and devices. In some embodiments, the techniques described herein relate to a transistor, including: a substrate including a first oxide material; an epitaxial oxide layer on the substrate including a second oxide material with a first bandgap; a gate layer on the epitaxial oxide layer, the gate layer including a third oxide material with a second bandgap, wherein the second bandgap is wider than the first bandgap; and electrical contacts. The second oxide material can include: one or two of Li, Ni, Al, Ga, Mg, and Zn; Ge; and O. The second oxide can also include (Ni.sub.xMg.sub.yZn.sub.1-x-y).sub.2GeO.sub.4 wherein 0x1 and 0y1. The electrical contacts can include: a source electrical contact coupled to the epitaxial oxide layer; a drain electrical contact coupled to the epitaxial oxide layer; and a first gate electrical contact coupled to the gate layer.

ULTRAWIDE BANDGAP SEMICONDUCTOR DEVICES INCLUDING MAGNESIUM GERMANIUM OXIDES
20240063271 · 2024-02-22 · ·

Various forms of Mg.sub.xGe.sub.1?xO.sub.2?x are disclosed, where an epitaxial layer comprises single crystal Mg.sub.xGe.sub.1?xO.sub.2?x, with x having a value of 0?x<1, wherein the single crystal Mg.sub.xGe.sub.1?xO.sub.2?x has a crystal symmetry compatible with a substrate or with an underlying layer on which the single crystal Mg.sub.xGe.sub.1?xO.sub.2?x is grown. Semiconductor structures and devices comprising the epitaxial layer of Mg.sub.xGe.sub.1?xO.sub.2?x are disclosed, along with methods of making the epitaxial layers and semiconductor structures and devices.

EPITAXIAL OXIDE MATERIALS, STRUCTURES, AND DEVICES
20240055560 · 2024-02-15 · ·

The present disclosure provides techniques for epitaxial oxide materials, structures and devices. In some embodiments, an integrated circuit includes a field effect transistor (FET) and a waveguide coupled to the FET, wherein the waveguide comprises a signal conductor. The FET can include: a substrate comprising a first oxide material; an epitaxial semiconductor layer on the substrate, the epitaxial semiconductor layer comprising a second oxide material with a first bandgap; a gate layer on the epitaxial semiconductor layer, the gate layer comprising a third oxide material with a second bandgap, wherein the second bandgap is wider than the first bandgap; and electrical contacts. The electrical contacts can include: a source electrical contact coupled to the epitaxial semiconductor layer; a drain electrical contact coupled to the epitaxial semiconductor layer; and a first gate electrical contact coupled to the gate layer.

Method of over current and over voltage protection of a power switch in combination with regulated DI/DT and DV/DT

A method for protecting a power switch during turn-on includes sensing that a change in current through the power switch is in regulation, measuring a time that the change in current through the power switch is in regulation, and comparing the time that the change in current through the power switch is in regulation to a reference time. An over current signal, which can be used to disable the power switch, is generated if the time that the change in current through the power switch is in excess of the reference time.

Advanced electronic device structures using semiconductor structures and superlattices

Semiconductor structures and methods for forming those semiconductor structures are disclosed. For example, a p-type or n-type semiconductor structure is disclosed. The semiconductor structure has a polar crystal structure with a growth axis that is substantially parallel to a spontaneous polarization axis of the polar crystal structure. The semiconductor structure changes in composition from a wider band gap (WBG) material to a narrower band gap (NBG) material or from a NBG material to a WBG material along the growth axis to induce p-type or n-type conductivity.

SELECTIVE GAS PHASE ETCH OF SILICON GERMANIUM ALLOYS

Methods for selective etching of one layer or material relative to another layer or material adjacent thereto. In an example, a SiGe layer is etched relative to or selective to another silicon containing layer which either contains no germanium or geranium in an amount less than that of the target layer.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
20190326420 · 2019-10-24 ·

Provided is a method for manufacturing a semiconductor device whose electric characteristics are prevented from being varied and whose reliability is improved. In the method, an insulating film is formed over an oxide semiconductor film, a buffer film is formed over the insulating film, oxygen is added to the buffer film and the insulating film, a conductive film is formed over the buffer film to which oxygen is added, and an impurity element is added to the oxide semiconductor film using the conductive film as a mask. An insulating film containing hydrogen and overlapping with the oxide semiconductor film may be formed after the impurity element is added to the oxide semiconductor film.