A semiconductor structure is provided. The semiconductor structure includes a substrate. The semiconductor structure also includes a buffer layer disposed on the substrate. The semiconductor structure further includes a first semiconductor layer disposed on the buffer layer. The buffer layer includes a first buffer structure and a second buffer structure partially disposed on the first buffer structure. The material of the first buffer structure is different from the material of the second buffer structure.

A method for making a multilayered device on an engineered substrate having a substrate coefficient of thermal expansion includes growing a buffer layer on the engineered substrate, and growing a first epitaxial layer on the buffer layer. The first epitaxial layer is characterized by an epitaxial coefficient of thermal expansion substantially equal to the substrate coefficient of thermal expansion.

Embodiments herein relate to chemical sensors, devices and systems including the same, and related methods. In an embodiment, a medical device is included having a graphene varactor including a graphene layer and a self-assembled monolayer disposed on an outer surface of the graphene layer through non-covalent interactions between the self-assembled monolayer and a -electron system of graphene. The self-assembled monolayer includes one or more pillarenes, substituted pillarenes, calixarenes, substituted calixarenes, peralkylated cyclodextrins, substituted peralkylated cyclodextrins, pyrenes, or substituted pyrenes, or derivatives thereof. Other embodiments are also included herein.

Embodiments of the present disclosure relate to forming a two-dimensional crystalline dichalcogenide by positioning a substrate in an annealing apparatus. The substrate includes an amorphous film of a transition metal and a chalcogenide. The film is annealed at a temperature from 500 C. to 1200 C. In response to the annealing, a two-dimensional crystalline structure is formed from the film. The two-dimensional crystalline structure is according to a formula MX.sub.2, M includes one or more of molybdenum (Mo) or tungsten (W) and X includes one or more of sulfur (S), selenium (Se), or tellurium (Te).

Methods, apparatuses, and systems related to formation of an atomic layer of germanium (Ge) on a substrate material are described. An example method includes introducing, into a semiconductor processing chamber housing a substrate material having a high aspect ratio, a reducing agent, and introducing, into the semiconductor processing chamber, a germanium amidinate precursor. The example method further includes forming an atomic layer of germanium on the substrate material resulting from a reaction of the reducing agent and the germanium amidinate precursor.

Embodiments described herein may be related to apparatuses, processes, and techniques directed to creating a transistor structure by selectively growing a 2D TMD directly in a stacked channel configuration, such as a stacked nanowire or nanoribbon formation. In embodiments, this TMD growth may occur for all of the nanowires or nanoribbons in the transistor structure in one stage. Placement of a SAM on a plurality of dielectric layers within the transistor structure stack facilitates channel deposition and channel geometry in the stacked channel configuration. Other embodiments may be described and/or claimed.

A method of fabricating a heterostructure system, comprises epitaxially growing a crystalline layer of a first substance on a crystalline base layer by surface catalysis in a solution, wherein the growth is self-terminated once a monolayer of the substance is formed on the base layer.

A silicon carbide epitaxial substrate includes a silicon carbide single crystal substrate and a silicon carbide layer. In a direction parallel to a central region, a ratio of a standard deviation of a carrier concentration of the silicon carbide layer to an average value of the carrier concentration of the silicon carbide layer is less than 5%. The average value of the carrier concentration is more than or equal to 110.sup.14 cm.sup.3 and less than or equal to 510.sup.16 cm.sup.3. In the direction parallel to the central region, a ratio of a standard deviation of a thickness of the silicon carbide layer to an average value of the thickness of the silicon carbide layer is less than 5%. The central region has an arithmetic mean roughness (Sa) of less than or equal to 1 nm. The central region has a haze of less than or equal to 50.

A method for making a semiconductor device may include forming a superlattice on a substrate comprising a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Moreover, forming at least one of the base semiconductor portions may include overgrowing the at least one base semiconductor portion and etching back the overgrown at least one base semiconductor portion.

The present invention discloses an epitaxial lift-off process of graphene-based gallium nitride (GaN), and principally solves the existing problems about complex lift-off technique, high cost, and poor quality of lift-off GaN films. The invention is achieved by: first, growing graphene on a well-polished copper foil by CVD method; then, transferring a plurality of layers of graphene onto a sapphire substrate; next, growing GaN epitaxial layer on the sapphire substrate with a plurality of graphene layers transferred by the metal organic chemical vapor deposition (MOCVD) method; finally, lifting off and transferring the GaN epitaxial layer onto a target substrate with a thermal release tape. With graphene, the present invention relieves the stress generated by the lattice mismatch between substrate and epitaxial layer; moreover, the present invention readily lifts off and transfers the epitaxial layer to the target substrate by means of weak Van der Waals forces between epitaxial layer and graphene.