The current disclosure describes semiconductor devices, e.g., transistors, including a substrate, a semiconductor region including, at the surface, monolayer MoS.sub.2 and/or other monolayer material over the substrate, and a terminal structure over the semiconductor region, which includes a different monolayer material grown directly over the semiconductor region.

A method of forming a silicon film in a recess formed in a target substrate includes: preparing a target substrate having a recess in which a plurality of different bases is exposed; forming an atomic layer seed on at least an inner surface of the recess by sequentially supplying a raw material gas adapted to the plurality of different bases and a reaction gas reacting with the raw material gas to the target substrate one or more times while heating the target substrate to a first temperature; and forming a silicon film on a surface of the atomic layer seed so as to fill the recess by supplying a first silicon raw material gas to the target substrate while heating the target substrate to a second temperature.

A method of forming nanocrystalline graphene by a plasma-enhanced chemical vapor deposition process is provided. The method of forming nanocrystalline graphene includes arranging a protective layer on a substrate and growing nanocrystalline graphene directly on the protective layer by using a plasma of a reaction gas. The reaction gas may include a mixed gas of a carbon source gas, an inert gas, and hydrogen gas.

A method includes depositing a copper layer over a first substrate, annealing the copper layer, depositing a hexagonal boron nitride (hBN) film on the copper layer, and removing the hBN film from the copper layer. The hBN film may be transferred to a second substrate.

A method for making a multilayered device on an engineered substrate having a substrate coefficient of thermal expansion includes growing a buffer layer on the engineered substrate, and growing a first epitaxial layer on the buffer layer. The first epitaxial layer is characterized by an epitaxial coefficient of thermal expansion substantially equal to the substrate coefficient of thermal expansion.

Provided are a graphene structure and a method of forming the graphene structure. The graphene structure includes a substrate and graphene on a surface of the substrate. Here, a bonding region in which a material of the substrate and carbon of the graphene are covalently bonded is formed between the surface of the substrate and the graphene.

A method for making a semiconductor device may include forming a superlattice on a substrate comprising a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Moreover, forming at least one of the base semiconductor portions may include overgrowing the at least one base semiconductor portion and etching back the overgrown at least one base semiconductor portion.

A method of fabricating semiconductor devices including epitaxially depositing a heavily doped substrate layer that is substantially free of crystalline defects on a lightly doped virtual substrate. The device regions of the semiconductor devices can be fabricated about the heavily doped substrate layer before the lightly doped virtual substrate is removed.

A method is provided that includes depositing a catalyst layer along a surface of the opening and performing a selectivity enhancement process. The selectivity enhancement process alters a deposition rate of a metal component on at least one region of the catalyst layer. The metal component is deposited on the catalyst layer. Exemplary selectivity enhancement processes include a self-assembled monolayer (SAM), introducing an accelerator, and/or introducing a suppressor.

A graphene-based layer transfer (GBLT) technique is disclosed. In this approach, a device layer including a III-V semiconductor, Si, Ge, III-N semiconductor, SiC, SiGe, or II-VI semiconductor is fabricated on a graphene layer, which in turn is disposed on a substrate. The graphene layer or the substrate can be lattice-matched with the device layer to reduce defect in the device layer. The fabricated device layer is then removed from the substrate via, for example, a stressor attached to the device layer. In GBLT, the graphene layer serves as a reusable and universal platform for growing device layers and also serves a release layer that allows fast, precise, and repeatable release at the graphene surface.