Patent classifications
H01L21/02505
POWER PHOTODIODE STRUCTURES, METHODS OF MAKING, AND METHODS OF USE
According to the present disclosure, techniques related to manufacturing and applications of power photodiode structures and devices based on group-III metal nitride and gallium-based substrates are provided. More specifically, embodiments of the disclosure include techniques for fabricating photodiode devices comprising one or more of GaN, AlN, InN, InGaN, AlGaN, and AlInGaN, structures and devices. Such structures or devices can be used for a variety of applications including optoelectronic devices, photodiodes, power-over-fiber receivers, and others.
METHOD TO CONTROL THE RELAXATION OF THICK FILMS ON LATTICE-MISMATCHED SUBSTRATES
A substrate comprising a III-N base layer comprising a first portion and a second portion, the first portion of the III-N base layer having a first natural lattice constant and a first dislocation density; and a first III-N layer having a second natural lattice constant and a second dislocation density on the III-N base layer, the first III-N layer having a thickness greater than 10 nm. An indium fractional composition of the first III-N layer is greater than 0.1; the second natural lattice constant is at least 1% greater than the first natural lattice constant; a strain-induced lattice constant of the first III-N layer is greater than 1.0055 times the first natural lattice constant; and the second dislocation density is less than 1.5 times the first dislocation density.
COMPOSITE SUBSTRATE AND MANUFACTURING METHOD THEREOF
A composite substrate is provided in some embodiments of the present disclosure, which includes a substrate, an insulation layer, a first silicon-containing layer and a first epitaxial layer. The insulation layer is disposed on the substrate. The first silicon-containing layer is disposed on the insulation layer, in which the first silicon-containing layer includes a plurality of group V atoms. The first epitaxial layer is disposed on the first silicon-containing layer, in which the first epitaxial layer includes a plurality of group III atoms. A distribution concentration of the group V atoms in the first silicon-containing layer increases as getting closer to the first epitaxial layer, and a distribution concentration of the group III atoms in the first epitaxial layer increases as getting closer to the first silicon-containing layer. A method of manufacturing a composite substrate is also provided in some embodiments of the present disclosure.
Composition and method for making picocrystalline artificial borane atoms
Materials containing picocrystalline quantum dots that form artificial atoms are disclosed. The picocrystalline quantum dots (in the form of born icosahedra with a nearly-symmetrical nuclear configuration) can replace corner silicon atoms in a structure that demonstrates both short range and long-range order as determined by x-ray diffraction of actual samples. A novel class of boron-rich compositions that self-assemble from boron, silicon, hydrogen and, optionally, oxygen is also disclosed. The preferred stoichiometric range for the compositions is (B.sub.12H.sub.w).sub.xSi.sub.yO.sub.z with 3≤w≤5, 2≤x≤4, 2≤y≤5 and 0≤z≤3. By varying oxygen content and the presence or absence of a significant impurity such as gold, unique electrical devices can be constructed that improve upon and are compatible with current semiconductor technology.
High electron mobility transistor (HEMT) device and method of forming same
A high electron mobility transistor (HEMT) device and a method of forming the same are provided. The method includes forming a first III-V compound layer over a substrate. A second III-V compound layer is formed over the first III-V compound layer. The second III-V compound layer has a greater band gap than the first III-V compound layer. A third III-V compound layer is formed over the second III-V compound layer. The third III-V compound layer and the first III-V compound layer comprise a same III-V compound. A passivation layer is formed along a topmost surface and sidewalls of the third III-V compound layer. A fourth III-V compound layer is formed over the second III-V compound layer. The fourth III-V compound layer has a greater band gap than the first III-V compound layer.
POROUS III-NITRIDES AND METHODS OF USING AND MAKING THEREOF
Porous III-nitrides having controlled/tuned optical, electrical, and thermal properties are described herein. Also disclosed are methods for preparing and using such porous III-nitrides.
Methods for Forming Stacked Layers and Devices Formed Thereof
A method includes etching a semiconductor substrate to form a trench, with the semiconductor substrate having a sidewall facing the trench, and depositing a first semiconductor layer extending into the trench. The first semiconductor layer includes a first bottom portion at a bottom of the trench, and a first sidewall portion on the sidewall of the semiconductor substrate. The first sidewall portion is removed to reveal the sidewall of the semiconductor substrate. The method further includes depositing a second semiconductor layer extending into the trench, with the second semiconductor layer having a second bottom portion over the first bottom portion, and a second sidewall portion contacting the sidewall of the semiconductor substrate. The second sidewall portion is removed to reveal the sidewall of the semiconductor substrate.
SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, and a carbonitride semiconductor layer. The first nitride semiconductor layer is over the substrate. The second nitride semiconductor layer is formed on the first nitride semiconductor layer and has a greater bandgap than that of the first nitride semiconductor layer. The carbonitride semiconductor layer is between the substrate and the first nitride semiconductor layer.
High breakdown voltage structure for high performance GaN-based HEMT and MOS devices to enable GaN C-MOS
An integrated circuit structure comprises a relaxed buffer stack that includes a channel region, wherein the relaxed buffer stack and the channel region include a group III-N semiconductor material, wherein the relaxed buffer stack comprises a plurality of AlGaN material layers and a buffer stack is located over over the plurality of AlGaN material layers, wherein the buffer stack comprises the group III-N semiconductor material and has a thickness of less than approximately 25 nm. A back barrier is in the relaxed buffer stack between the plurality of AlGaN material layers and the buffer stack, wherein the back barrier comprises an AlGaN material of approximately 2-10% Al. A polarization stack over the relaxed buffer stack.
SEMICONDUCTOR DEVICE STRUCTURES AND METHODS OF MANUFACTURING THE SAME
Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first layer and a second layer. The first layer is disposed on and in contact with the substrate. The first layer includes Al.sub.X1Ga.sub.(1-X1)N, wherein 0.5≤X1<1. The second layer is disposed on and in contact with the first layer. The second layer includes Al, Ga and N.