The present invention provides a semiconductor device, comprising: a substrate (10); a stack of III-nitride transition layers (11) disposed on the substrate (10), the stack of III-nitride transition layers (11) maintaining an epitaxial relationship to the substrate (10); a first III-nitride layer (121) disposed on the stack of III-nitride transition layers (11); and a second III-nitride layer (122) disposed on the first III-nitride layer (121), the second III-nitride layer (122) having a band gap energy greater than that of the first III-nitride layer (121), wherein the stack of III-nitride transition layers (11) comprises a first transition layer (111), a second transition layer (112) on the first transition layer (111), and a third transition layer (113) on the second transition layer (112), and wherein the second transition layer (112) has a minimum aluminium molar ratio among the first transition layer (111), the second transition layer (112) and third transition layer (113). The present invention also relates to a method of forming such semiconductor device. The semiconductor device according to the present invention advantageously has a dislocation density less than or equal to 1×10.sup.9 cm.sup.−2 in the first III-nitride layer (121).

A semiconductor structure includes a substrate. The semiconductor structure further includes a buffer layer over the substrate, wherein the buffer layer comprises a plurality of III-V layers, and a dopant type of each III-V layer of the plurality of III-V layers is opposite to a dopant of adjacent III-V layers of the plurality of III-V layers. The semiconductor structure further includes an active layer over the buffer layer. The semiconductor structure further includes a dielectric layer over the active layer.

An epitaxial wafer according to the present disclosure includes: a substrate; a buffer layer formed of a crystal having the composition formula represented by Al.sub.xGa.sub.yIn.sub.zN (x+y+z=1, y>0) on the substrate; a back-barrier layer formed of a crystal having the composition formula represented by Al.sub.xGa.sub.yIn.sub.zN (x+y+z=1, y>0, z>0) on the buffer layer; a channel layer formed of a crystal having the composition formula represented by Al.sub.xGa.sub.yIn.sub.zN (x+y+z=1, y>0) on the back-barrier layer; and an electron-supply layer formed of a crystal having the composition formula represented by Al.sub.xGa.sub.yIn.sub.zN (x+y+z=1, x>0) on the channel layer. The channel layer is constituted with an upper channel layer underneath the electron-supply layer and a lower channel layer on the back-barrier layer, and the lower channel layer has a C concentration higher than the upper channel layer and contains Si.

The present disclosure provides a semiconductor structure and a method of forming the same. A semiconductor structure according to the present disclosure includes a plurality of nanostructures disposed over a substrate and a gate structure wrapping around each of the plurality of nanostructure. Each of the plurality of nanostructures includes a channel layer sandwiched between two cap layers along a direction perpendicular to the substrate.

Various embodiments of the present application are directed towards a group III-V device including a rough buffer layer. The rough buffer layer overlies a silicon substrate, a buffer structure overlies the rough buffer layer, and a heterojunction structure overlies the buffer structure. The buffer structure causes band bending and formation of a two-dimensional hole gas (2DHG) in the rough buffer layer. The rough buffer layer includes silicon or some other suitable semiconductor material and, in some embodiments, is doped. A top surface of the rough buffer layer and/or a bottom surface of the rough buffer layer is/are rough to promote carrier scattering along the top and bottom surfaces. The carrier scattering reduces carrier mobility and increases resistance at the 2DHG. The increased resistance increases an overall resistance of the silicon substrate, which reduces substrate loses and increases a power added efficiency (PAE).

Embodiments of the present invention provide a semiconductor device capable of improving both the thermal stability and contact resistance and a method for fabricating the same. According to an embodiment of the present invention, a semiconductor device may comprise: a contact plug over a substrate, wherein the contact plug includes: a silicide layer having a varying carbon content in a film, and a metal material layer over the silicide layer.

An epitaxial structure includes a substrate, a nucleation layer on the substrate, a buffer layer on the nucleation layer, and a nitride layer on the buffer layer. The nucleation layer consists of regions in a thickness direction, wherein a chemical composition of the regions is Al.sub.(1-x)In.sub.xN, where 0≤x≤1. A maximum value of the x value in the plurality of regions is the same, a minimum value of the x value in the plurality of regions is the same, and an absolute value of a gradient slope of each of the regions is 0.1%/nm to 50%/nm. A thickness of the nucleation layer is less than a thickness of the buffer layer. A roughness of a surface of the nucleation layer in contact with the buffer layer is greater than a roughness of a surface of the buffer layer in contact with the nitride layer.

A film forming method includes: forming a laminated film, in which an interface layer, a bulk layer, and a surface layer are laminated in this order, on a base; and crystallizing the laminated film, wherein the bulk layer is formed of a film that is easier to crystallize than the interface layer in crystallizing the laminated film, and wherein the surface layer is formed of a film that is easier to crystallize than the bulk layer in crystallizing the laminated film.

A process for the production of a layer structure of a nitride semiconductor component on a silicon surface, comprising: provision of a substrate having a silicon surface; deposition of an aluminium-containing nitride nucleation layer on the silicon surface of the substrate; optional: deposition of an aluminium-containing nitride buffer layer on the nitride nucleation layer; deposition of a masking layer on the nitride nucleation layer or, if present, on the first nitride buffer layer; deposition of a gallium-containing first nitride semiconductor layer on the masking layer, wherein the masking layer is deposited in such a way that, in the deposition step of the first nitride semiconductor layer, initially separate crystallites grow that coalesce above a coalescence layer thickness and occupy an average surface area of at least 0.16 μm.sup.2 in a layer plane of the coalesced nitride semiconductor layer that is perpendicular to the growth direction.

Systems and methods are described herein to include an epitaxial metal layer between a rare earth oxide and a semiconductor layer. Systems and methods are described to grow a layered structure, comprising a substrate, a first rare earth oxide layer epitaxially grown over the substrate, a first metal layer epitaxially grown over the rare earth oxide layer, and a first semiconductor layer epitaxially grown over the first metal layer. Specifically, the substrate may include a porous portion, which is usually aligned with the metal layer, with or without a rare earth oxide layer in between.