Patent classifications
H01L21/0251
Method for fabricating a monocrystalline structure
A substrate is provided with a monocrystalline silicon-germanium layer with a first surface covered by a protective oxide obtained by wet process and having a degradation temperature. The protective oxide is transformed into fluorinated salt which is then eliminated. The substrate is placed in a processing chamber at a lower temperature than the degradation temperature and is subjected to a temperature ramp up to a higher temperature than the degradation temperature. The first surface is annealed in a hydrogen atmosphere devoid of silicon, germanium and precursors of the materials forming the target layer. When the temperature ramp is applied, a silicon precursor is inserted in the processing chamber between a loading temperature and the degradation temperature to deposit a monocrystalline buffer layer. A mono-crystalline target layer is deposited by chemical vapour deposition.
Metamorphic solar cells
A multijunction solar cell including a metamorphic layer, and particularly the design and specification of the composition, lattice constant, and band gaps of various layers above the metamorphic layer in order to achieve reduction in “bowing” of the semiconductor wafer caused by the lattice mismatch of layers associated with the metamorphic layer.
THIN FILM TRANSISTOR INCLUDING A COMPOSITIONALLY-GRADED GATE DIELECTRIC AND METHODS FOR FORMING THE SAME
A thin film transistor may be manufactured by forming a gate electrode in an insulating layer over a substrate, forming a gate dielectric over the gate electrode and the insulating layer, forming an active layer over the gate electrode, and forming a source electrode and a drain electrode contacting a respective portion of a top surface of the active layer. A surface oxygen concentration may be increased in at least one of the gate dielectric and the active layer by introducing oxygen atoms into a surface region of a respective one of the gate dielectric and the active layer.
SEMICONDUCTOR DEVICE WITH STRAIN RELAXED LAYER
A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.
EPITAXIAL STRUCTURE
An epitaxial structure includes a substrate, a nucleation layer on the substrate, a buffer layer on the nucleation layer, and a nitride layer on the buffer layer. The nucleation layer consists of regions in a thickness direction, wherein a chemical composition of the regions is Al.sub.(1−X)In.sub.XN, where 0≤x≤1. A maximum value of the x value in the regions decreases along the thickness direction, and the x value in the chemical composition of each two regions consists of a fixed region and a gradient region, wherein a gradient slope of the gradient regions is −0.1%/nm to −50%/nm, and a stepwise slope of the fixed regions is −0.1%/loop to −50%/loop. A thickness of the nucleation layer is less than that of the buffer layer. A surface roughness of the nucleation layer in contact with the buffer layer is greater than that of the buffer layer in contact with the nitride layer.
EPITAXIAL STRUCTURE
An epitaxial structure includes a substrate, a nucleation layer, a buffer layer, and a nitride layer orderly. The nucleation layer consists of regions in a thickness direction, wherein a chemical composition of the regions is Al.sub.(1−x)In.sub.xN, where 0≤x≤1. The x value consists of four sections of variation along the thickness direction, in which a first fixed region has a maximum value, a first gradient region gradually changes from the maximum value to a minimum value, a second fixed region has the minimum value, and a second gradient region gradually changes from the minimum value to the maximum value. An absolute value of a gradient slope of the first and second gradient regions is 0.1%/nm to 50%/nm. A surface roughness of the nucleation layer in contact with the buffer layer is greater than that of the buffer layer in contact with the nitride layer.
EPITAXIAL STRUCTURE
An epitaxial structure includes a substrate, a nucleation layer on the substrate, a buffer layer on the nucleation layer, and a nitride layer on the buffer layer. The nucleation layer consists of regions in a thickness direction, wherein a chemical composition of the regions is Al.sub.(1-x)In.sub.xN, where 0≤x≤1. A maximum value of the x value in the plurality of regions is the same, a minimum value of the x value in the plurality of regions is the same, and an absolute value of a gradient slope of each of the regions is 0.1%/nm to 50%/nm. A thickness of the nucleation layer is less than a thickness of the buffer layer. A roughness of a surface of the nucleation layer in contact with the buffer layer is greater than a roughness of a surface of the buffer layer in contact with the nitride layer.
COMPOUND SEMICONDUCTOR SUBSTRATE
A compound semiconductor substrate that can improve in-plane uniformity of current-voltage characteristics in the vertical direction is provided.
A compound semiconductor substrate includes a center and an edge which is 71.2 millimeters away from the center when viewed in a plane. When a film thickness of the GaN layer at the center of the compound semiconductor substrate is W1 and a film thickness of the CaN layer at the edge is W2, film thickness error ΔW represented by ΔW (%)=W1−W2|*100/W1 is greater than 0 and 8% or less. The average carbon concentration in the depth direction at a center of the CaN layer is 3*10.sup.18 pieces/cm.sup.3 or more and 5*10.sup.20 pieces/cm.sup.3 or less. When a carbon concentration at a center position of the depth direction at the center of the GaN layer is concentration C1 and a carbon concentration at a center position of the depth direction at the edge of the GaN layer is concentration C2, concentration error ΔC represented by ΔC (%)=|C1−C2*100/C1 is 0 or more and 50% or less.
COMPOUND SEMICONDUCTOR SUBSTRATE
A compound semiconductor substrate has a Si (silicon) substrate, a first Al nitride semiconductor layer which is a graded layer formed on the Si substrate and whose Al concentration decreases as the distance from the Si substrate increases along the thickness direction, a GaN (gallium nitride) layer formed on the first Al nitride semiconductor layer and having a lower average Al concentration than the average Al concentration of the first Al nitride semiconductor layer, and a second Al nitride semiconductor layer formed on the GaN layer and having a higher average Al concentration than the average Al concentration of the GaN layer. The threading dislocation density at any position in the thickness direction within the second Al nitride semiconductor layer is lower than the threading dislocation density at any position in the thickness direction within the first Al nitride semiconductor layer.
SEMICONDUCTOR DEVICE WITH STRAIN RELAXED LAYER
A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.