Provided is a field effect transistor including a gate insulating layer having a two-dimensional material. The field effect transistor may include a first channel layer; a second channel layer disposed on the first channel layer; a gate insulating layer disposed on the second channel layer; a gate electrode disposed on the gate insulating layer; a first electrode electrically connected to the first channel layer; and a second electrode electrically connected to the second channel layer. Here, the gate insulating layer may include an insulative, high-k, two-dimensional material.

A doped diamond semiconductor and method of production using a laser is disclosed herein. As disclosed, a dopant and/or a diamond or sapphire seed material may be added to a graphite based ablative layer positioned below a confinement layer, the ablative layer also being graphite based and positioned above a backing layer, to promote formation of diamond particles having desirable semiconductor properties via the action of a laser beam upon the ablative layer. Dopants may be incorporated into the process to activate the reaction sought to produce a material useful in production of a doped semiconductor or a doped conductor suitable for the purpose of modulating the electrical, thermal or quantum properties of the material produced. As disclosed, the diamond particles formed by either the machine or method of confined pulsed laser deposition disclosed may be arranged as semiconductors, electrical components, thermal components, quantum components and/or integrated circuits.

The present invention relates to a method for assembling molecules on the surface of a two-dimensional material formed on a substrate, the method comprises: forming a spacer layer comprising at least one of an electrically insulating compound or a semiconductor compound on the surface of the two-dimensional material, depositing molecules on the spacer layer, annealing the substrate with spacer layer and the molecules at an elevated temperature for an annealing time duration, wherein the temperature and annealing time are such that at least a portion of the molecules are allowed to diffuse through the spacer layer towards the surface of the two-dimensional material to assemble on the surface of the two-dimensional material. The invention also relates to an electronic device.

Methods and apparatus for depositing carbon nanostructures such as three-dimensional graphene mesh using non-equilibrium gaseous plasma of high power density. Methods are disclosed for rapid deposition of randomly distributed graphene sheets on surfaces of substrates using decomposition of CO molecules of a high potential energy, and said excited CO molecules interacting with a substrate. The three-dimensional graphene mesh prepared according to the methods are useful in different applications such as light absorbents, fuel cells, super-capacitors, batteries, photovoltaic devices and sensors of specific gaseous molecules.

A substrate processing apparatus includes: configured to support a plurality of substrates; a chamber sidewall surrounding at least a side surface of the substrate support; and an upper plate including a plurality of plate portions on the substrate support and spaced apart from the substrate support. The plurality of plate portions and the substrate support collectively at least partially define a plurality of process regions between the plurality of plate portions and the substrate support and a separation between at least two process regions of the plurality of process regions. The plurality of process regions include a pretreatment process region between the pretreatment process plate portion and the substrate support and having a first height, and a deposition process region between the deposition process plate portion and the substrate support and having a second height, greater than the first height.

In certain examples, methods and semiconductor structures are directed to a method comprising steps of forming by monolithically integrating or seeding via polycrystalline diamond (PCD) particles on a GaN-based layer characterized as including GaN in at least a surface region of the GaN-based layer. After the step of seeding, the PCD particles are grown under a selected pressure to form a diamond layer section and to provide a semi-conductive structure that includes the diamond layer section integrated on or against the surface region of the GaN-based layer.

In order to enable simple removal of a substrate used for manufacturing a semiconductor element, a manufacturing method includes forming a graphene layer on a substrate portion formed of a semiconductor, forming an element portion on the graphene layer, the element portion including a semiconductor layer directly formed on the graphene layer, which takes over crystal information relating to the substrate portion when the semiconductor layer is formed on the substrate portion without intermediation of the graphene layer, and performing cutting-off between the substrate portion and the element portion at the graphene layer.

Disclosed is a method for preparing a graphyne including: supplying a precursor represented by the following Chemical Formula 1 to a chamber including a first zone and a second zone; vaporizing or subliming the precursor in the first zone; and depositing the precursor vaporized or sublimed in the second zone on a metal substrate to form the graphyne:

##STR00001## (in Chemical Formula 1, X is carbon or nitrogen, and R.sub.1 to R.sub.3 may be selected from the group consisting of hydrogen, bromine, fluorine, chlorine, and iodine, respectively).

A multilayer diamond system includes an optically transparent substrate and an optically transparent intermediate layer deposited on the optically transparent substrate. A diamond layer is deposited on the optically transparent intermediate layer and formed from diamond having at least 50% of diamond grains sized between 2 nm and 500 nanometers.

Provided is a landing pad structure including a substrate, a plurality of landing pads, a guard ring, and an edge pattern. The substrate includes a cell region, a periphery region, and a guard ring region located between the cell region and the periphery region. The landing pads are arranged on the substrate in the cell region in a hexagonal close packing (HCP) configuration. The guard ring is disposed on the substrate in the guard ring region in a strip form. The edge pattern is disposed on the substrate in the cell region and close to the guard ring region. A method of manufacturing the landing pad structure is also provided.