Apparatus, systems, and methods for tuning the structure, conductivity, and/or wettability of laser induced graphene for a variety of functions including but not limited to multiplexed open microfluidic environmental biosensing and energy storage devices. Aspects of this invention introduce a one-step, mask-free process to create, pattern, and tune laser-induced graphene (LIG) with a ubiquitous CO2 laser or other laser. The laser parameters are adjusted to create LIG with different electrical conductivity, surface morphology, and surface wettability without the need for post chemical modification. This can be done with a single lasing. By optionally introducing a second (or third, fourth, or more) lasing(s), the LIG characteristics can be changed in just the same one step of using the laser scribing without other machines or sub-systems. One example is a second lasing with the same laser sub-system at low laser power, wherein the wettability of the LIG can be significantly altered. Such films presented unique superhydrophobicity owing to the combination of the micro/nanotextured structure and the removal of the hydrophilic oxygen-containing functional groups. The ability to tune the wettability of LIG while retaining high electrical conductivity and mechanical robustness allows rational design of LIG based on application.

A substrate processing method includes: a carry-in step of carrying a substrate having a silicon-containing film on a surface of the substrate into a processing container; a first step of forming an adsorption layer by supplying an oxygen-containing gas into the processing container and causing the oxygen-containing gas to be adsorbed on a surface of the silicon-containing film; a second step of forming a silicon oxide layer by supplying an argon-containing gas into the processing container and causing the adsorption layer and the surface of the silicon-containing film to react with each other with plasma of the argon-containing gas; and a third step of forming a graphene film on the silicon oxide layer by supplying a carbon-containing gas into the processing container with plasma of the carbon-containing gas.

Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The method may include the steps of selecting a diamond semiconductor material having a surface, exposing the surface to a source gas in an etching chamber, forming a carbide interface contact layer on the surface; and forming a metal layer on the interface layer.

Methods for depositing an amorphous carbon layer onto a substrate, including over previously formed layers on the substrate, use a plasma-enhanced chemical vapor deposition (PECVD) process. In particular, the methods utilize a combination of RF AC power and pulsed DC power to create a plasma which deposits an amorphous carbon layer with a high ratio of sp3 (diamond-like) carbon to sp2 (graphite-like) carbon. The methods also provide for lower processing pressures, lower processing temperatures, and higher processing powers, each of which, alone or in combination, may further increase the relative fraction of sp3 carbon in the deposited amorphous carbon layer. As a result of the higher sp3 carbon fraction, the methods provide amorphous carbon layers having improved density, rigidity, etch selectivity, and film stress as compared to amorphous carbon layers deposited by conventional methods.

Methods for treating a thin film made from a conductive or semiconductive material may improve the crystalline quality thereof. Such methods may include: supplying a substrate including, on one of the faces thereof, a thin film of the material; and biased plasma treating the assembly formed by the substrate and the thin film at a given temperature and for a given time, so as to obtain a crystalline reorganization over a depth of the thin film, the biased plasma treatment including an electrical biasing of the thin film and an exposure of the film thus biased to a hydrogen plasma, the biased plasma treatment being implemented at a temperature that is below the melting points of the thin film and of the substrate.

A transistor includes a channel layer, a gate stack, and source/drain regions. The channel layer includes a graphene layer and hexagonal boron nitride (hBN) flakes dispersed in the graphene layer. Orientations of the hBN flakes are substantially aligned. The gate stack is over the channel layer. The source/drain regions are aside the gate stack.

A semiconductor device includes a substrate, a semiconductor structure suspending over the substrate and comprising a source region, a drain region, and a channel region disposed between the source region and the drain region. The channel region includes a doped two-dimensional (2D) material layer comprising a first portion on an upper surface of the channel region. The semiconductor device also includes an interfacial layer surrounding the channel region including the first portion of the doped 2D material layer, and and a gate electrode surrounding the interfacial layer.

Embodiments of this application provide a semiconductor structure, an electronic device, and a manufacture method for a semiconductor structure, and relate to the field of heat dissipation technologies for electronic products. An example semiconductor structure includes a semiconductor device, a bonding layer, a substrate, a conducting via, and a metal layer. The semiconductor device is disposed on an upper surface of the substrate by using the bonding layer. The metal layer is disposed on a lower surface of the substrate. The substrate includes a base plate, a groove formed on the base plate, and a diamond accommodated in the groove. The conducting via penetrates the substrate, the bonding layer, and at least a part of the semiconductor device, and is electrically connected to the metal layer. The groove bypasses the conducting via.

This application relates to a pellicle for extreme ultraviolet lithography and a manufacturing method thereof using the low-temperature direct growth method of multilayer graphene. In one aspect, the method includes forming an etch stopper on a substrate, forming a seed layer on the etch stopper, the seed layer including at least one of amorphous boron, BN, BCN, B.sub.4C, or Me-X (Me is at least one of Si, Ti, Mo, or Zr, and X is at least one of B, C, or N). The method may also include forming a metal catalyst layer on the seed layer; forming an amorphous carbon layer on the metal catalyst layer, and directly growing multilayer graphene on the seed layer through interlayer exchange between the metal catalyst layer and the amorphous carbon layer by performing a low-temperature heat treatment at 450° C. to 600° C.

Provided are a graphene interconnect structure, an electronic device including the graphene interconnect structure, and a method of manufacturing the graphene interconnect structure. The graphene interconnect structure may include: a first oxide dielectric material layer; a second oxide dielectric material layer on a surface of the first oxide dielectric material layer and having a dielectric constant greater than that of the first oxide dielectric material layer; and a graphene layer on a surface of the second oxide dielectric material layer opposite to the surface on which the first oxide dielectric material layer is located.