A reinforced thin-film device (100, 200, 500) including a substrate (101) having a top surface for supporting an epilayer; a mask layer (103) patterned with a plurality of nanosize cavities (102, 102′) disposed on said substrate (101) to form a needle pad; a thin-film (105) of lattice-mismatched semiconductor disposed on said mask layer (103), wherein said thin-film (105) comprises a plurality of in parallel spaced semiconductor needles (104, 204) of said lattice-mismatched semiconductor embedded in said thin-film (105), wherein said plurality of semiconductor needles (104, 204) are substantially vertically disposed in the axial direction toward said substrate (101) in said plurality of nanosize cavities (102, 102′) of said mask layer (103), and where a lattice-mismatched semiconductor epilayer (106) is provided on said thin-film supported thereby.

Provided are a two-dimensional material structure, a semiconductor device including the two-dimensional material structure, and a method of manufacturing the semiconductor device. The two-dimensional material structure may include a first insulator including a first dielectric material; a second insulator on the first insulator and including a second dielectric material; a first two-dimensional material film on an exposed surface of the first insulator; and a second two-dimensional material film provided on an exposed surface of the second insulator. The first and second two-dimensional material films may include a two-dimensional material having a two-dimensional layered structure, and the second two-dimensional material film may include more layers of the two-dimensional material than the first two-dimensional material film.

A method for manufacturing a compound semiconductor substrate that can achieve thinning of SiC film, wherein the method includes forming a SiC film on one principal surface side of a Si substrate and forming a recessed part in which a bottom surface is Si in a central part of another principal surface of the Si substrate.

Provided are a graphene structure and a method of forming the graphene structure. The graphene structure includes a substrate and graphene on a surface of the substrate. Here, a bonding region in which a material of the substrate and carbon of the graphene are covalently bonded is formed between the surface of the substrate and the graphene.

A method of addressing at least one qubit to be addressed in a set of two or more qubits includes exposing the qubit to be addressed to an electromagnetic field; and at a same time exposing another qubit of the set of two or more qubits to an electromagnetic counter field in such a way that the electromagnetic field has no effect on the other qubit or that the electromagnetic field has a different effect on the other qubit than on the qubit to be addressed. A device for performing the method includes the set of two or more qubits and electromagnetic sources for generating the electromagnetic field and electromagnetic counter field.

Provided are a field effect transistor, an electronic apparatus including the same, and a method of manufacturing the field effect transistor. The field effect transistor may include a substrate; a gate electrode on the substrate; an insulating layer on the gate electrode; a source electrode on the insulating layer; a drain electrode apart from the source electrode; a channel between the source electrode and the drain electrode and including a two-dimensional (2D) material; a 2D material electrode bonding layer adjacent to the source electrode and the drain electrode; and a stressor adjacent to the 2D material electrode bonding layer. The stressor may be configured to apply a tensile strain to the 2D material electrode bonding layer.

By widening a terrace on a crystal surface on a bottom face of a recess by step flow caused by heating, a flat face is formed on the bottom face of the recess, a two-dimensional material layer made of a two-dimensional material is formed on the formed flat face, and then a device made of the two-dimensional material layer is produced.

A method for making a field effect transistor includes providing a graphene nanoribbon composite structure. The graphene nanoribbon composite structure includes a substrate and a plurality of graphene nanoribbons spaced apart from each other. The plurality of graphene nanoribbons are located on the substrate and extend substantially along a same direction, and each of the plurality of graphene nanoribbons includes a first end and a second end opposite to the first end. A source electrode is formed on the first end, and a drain electrode is formed on the second end. The source electrode and the drain electrode are electrically connected to the plurality of graphene nanoribbons. An insulating layer is formed on the plurality of graphene nanoribbons, and the plurality of graphene nanoribbons are between the insulating layer and the substrate. A gate is formed on a surface of the insulating layer away from the substrate.

Wafers including a diamond layer and a semiconductor layer having III-Nitride compounds and methods for fabricating the wafers are provided. A nucleation layer, at least one semiconductor layer having III-Nitride compound and a protection layer are formed on a silicon substrate. Then, a silicon carrier wafer is glass bonded to the protection layer. Subsequently the silicon substrate, nucleation layer and a portion of the semiconductor layer are removed. Then, an intermediate layer, a seed layer and a first diamond layer are sequentially deposited on the III-Nitride layer. Next, the silicon carrier wafer and the protection layer are removed. Then, a silicon substrate wafer that includes a protection layer, silicon substrate and a diamond layer is prepared and glass bonded to the first diamond layer.

Provided are a diamond field effect transistor using a silicon oxide film as a gate insulating film including a silicon-terminated layer containing C—Si bonds in order to reduce an interface state density, and a method for producing the same. A FET 100A includes a silicon oxide film 3A formed on a surface of a non-doped diamond layer 2A, a non-doped diamond layer 4A formed on a surface of the non-doped diamond layer 2A using the silicon oxide film 3A as a mask, a silicon-terminated layer 5A formed at an interface between the non-doped diamond layer 2A and the silicon oxide film 3A and at an interface between the non-doped diamond layer 4A and the silicon oxide film 3A, and a gate electrode 12A formed on the silicon oxide film 3A. The FET 100A operates using the silicon oxide film 3A and an insulating film 10A formed on the silicon oxide film 3A as a gate insulating film 11A and using the non-doped diamond layer 4A as each of a source region and a drain region.