FIELD EFFECT TRANSISTOR, ELECTRONIC APPARATUS INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE FIELD EFFECT TRANSISTOR

Abstract

Provided are a field effect transistor, an electronic apparatus including the same, and a method of manufacturing the field effect transistor. The field effect transistor may include a substrate; a gate electrode on the substrate; an insulating layer on the gate electrode; a source electrode on the insulating layer; a drain electrode apart from the source electrode; a channel between the source electrode and the drain electrode and including a two-dimensional (2D) material; a 2D material electrode bonding layer adjacent to the source electrode and the drain electrode; and a stressor adjacent to the 2D material electrode bonding layer. The stressor may be configured to apply a tensile strain to the 2D material electrode bonding layer.

Claims

1. A field effect transistor comprising: a substrate; a gate electrode on the substrate; an insulating layer on the gate electrode; a source electrode on the insulating layer; a drain electrode spaced apart from the source electrode; a channel between the source electrode and the drain electrode and comprising a two-dimensional (2D) material; a 2D material electrode bonding layer adjacent to the source electrode and the drain electrode and comprising a tensile strain region; and a stressor adjacent to the 2D material electrode bonding layer and configured to apply a tensile strain to the 2D material electrode bonding layer.

2. The field effect transistor of claim 1, wherein the 2D material electrode bonding layer comprises graphene, black phosphorus, phosphorene, or transition metal dichalcogenide.

3. The field effect transistor of claim 2, wherein the 2D material electrode bonding layer comprises the transition metal dichalcogenide, the transition metal dichalcogenide comprises a transition metal and a chalcogen element, the transition metal includes one of Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, Cu, Ga, In, Sn, Ge, and Pb, and the chalcogen element includes one of S, Se, and Te.

4. The field effect transistor of claim 2, wherein the transition metal dichalcogenide comprises one of MoS.sub.2, WS.sub.2, MoSe.sub.2, and WSe.sub.2.

5. The field effect transistor of claim 1, wherein the channel is configured to have no tensile strain region.

6. The field effect transistor of claim 1, wherein the 2D material electrode bonding layer is integrally provided with the channel.

7. The field effect transistor of claim 1, wherein the stressor is positioned above the 2D material electrode bonding layer, below the 2D material electrode bonding layer, or below the source electrode and the drain electrode.

8. The field effect transistor of claim 1, wherein the stressor comprises a material represented by (M1).sub.a(M2).sub.b, wherein M1 comprises any one of Mo, W, Hf, Nb, and Si, M2 comprises any one of O, S, Se, Te, and N, 0<a≤3, and 0<b≤3.

9. The field effect transistor of claim 8, wherein the stressor comprises MoO, MoO.sub.2, MoO.sub.3, PtS.sub.2, SiO.sub.2, or SiN.

10. The field effect transistor of claim 1, wherein the 2D material electrode bonding layer comprises a strain region in a region facing the stressor.

11. The field effect transistor of claim 1, further comprising: an interlayer between the 2D material electrode bonding layer and the stressor, wherein the interlayer comprises TiOx (0<x≤3) or CrOx (0<x≤3).

12. The field effect transistor of claim 1, wherein the stressor is configured to operate as an electrode.

13. The field effect transistor of claim 1, wherein the tensile strain region is in the 2D material electrode bonding layer.

14. An electronic apparatus comprising: a memory comprising a field effect transistor; and a memory controller configured to control the memory, wherein the field effect transistor comprises a substrate, a gate electrode on the substrate, an insulating layer on the gate electrode, a source electrode on the insulating layer, a drain electrode spaced apart from the source electrode, a channel between the source electrode and the drain electrode and comprising a two-dimensional (2D) material, a 2D material electrode bonding layer adjacent to the source electrode and the drain electrode and comprising a tensile strain region, and a stressor adjacent to the 2D material electrode bonding layer and configured to apply a tensile strain to the 2D material electrode bonding layer.

15. The electronic apparatus of claim 14, wherein the 2D material electrode bonding layer comprises graphene, black phosphorus, phosphorene, or transition metal dichalcogenide.

16. The electronic apparatus of claim 15, wherein the transition metal dichalcogenide comprises one of MoS.sub.2, WS.sub.2, MoSe.sub.2, and WSe.sub.2.

17. The electronic apparatus of claim 14, wherein the channel is configured to have no tensile strain region.

18. The electronic apparatus of claim 14, wherein the 2D material electrode bonding layer is integrally provided with the channel.

19. The electronic apparatus of claim 14, wherein the stressor is positioned above the 2D material electrode bonding layer, below the 2D material electrode bonding layer, or below the source electrode and the drain electrode.

20. The electronic apparatus of claim 14, wherein the stressor comprises a material represented by (M1).sub.a(M2).sub.b, wherein M1 comprises any one of Mo, W, Hf, Nb, and Si, M2 comprises any one of O, S, Se, Te, and N, 0<a≤3, and 0<b≤3.

21. The electronic apparatus of claim 14, wherein the stressor comprises MoO, MoO.sub.2, MoO.sub.3, PtS.sub.2, SiO.sub.2, or SiN.

22. A method of manufacturing a field effect transistor, the method comprising: forming a gate electrode on a substrate; forming an insulating layer on the gate electrode; forming a source electrode and a drain electrode on the insulating layer; forming a channel between the source electrode and the drain electrode, the channel comprising a two-dimensional (2D) material; forming a 2D material electrode bonding layer adjacent to the source electrode and the drain electrode; forming a stressor adjacent to the 2D material electrode bonding layer; and applying a tensile strain to the 2D material electrode bonding layer by oxidizing the stressor.

23. The method of claim 22, wherein the 2D material electrode bonding layer comprises graphene, black phosphorus, phosphorene, or transition metal dichalcogenide.

24. The method of claim 23, wherein the 2D material electrode bonding layer comprises the transition metal dichalcogenide, and the transition metal dichalcogenide comprises one of MoS.sub.2, WS.sub.2, MoSe.sub.2, and WSe.sub.2.

25. The method of claim 22, wherein the channel is configured to have no tensile strain region.

26. The method of claim 22, wherein the stressor is positioned above the 2D material electrode bonding layer, below the 2D material electrode bonding layer, or below the source electrode and the drain electrode.

27. The method of claim 22, wherein the stressor comprises a material represented by (M1).sub.a(M2).sub.b, wherein M1 comprises any one of Mo, W, Hf, Nb, and Si, M2 comprises any one of O, S, Se, Te, and N, 0<a≤3, and 0<b≤3.

28. The method of claim 22, wherein the stressor comprises MoO, MoO.sub.2, MoO.sub.3, PtS.sub.2, SiO.sub.2, or SiN.

29. A field effect transistor comprising: a substrate; a plurality of electrodes including a source electrode, a drain electrode, and a gate electrode spaced apart from each other on the substrate; a channel on the substrate between the source electrode and the drain electrode, the channel comprising a two-dimensional (2D) material; an insulating layer extending between the channel and the gate electrode; a first 2D material electrode bonding layer connected to a first end of the channel, the first 2D material electrode bonding layer being spaced apart from the gate electrode and the drain electrode; and a first stressor on at least one of the insulating layer and the source electrode, the first stressor adjacent to the first 2D material electrode bonding layer and configured to apply a tensile strain to the first 2D material electrode bonding layer.

30. The field effect transistor of claim 29, wherein the first 2D material electrode bonding layer comprises graphene, black phosphorus, phosphorene, or transition metal dichalcogenide.

31. The field effect transistor of claim 29, wherein the first stressor comprises a material represented by (M1).sub.a(M2).sub.b, wherein M1 comprises any one of Mo, W, Hf, Nb, and Si, M2 comprises any one of O, S, Se, Te, and N, 0<a≤3, and 0<b≤3.

32. The field effect transistor of claim 29, wherein the first 2D material electrode bonding layer is integrally provided with the channel.

33. The field effect transistor of claim 29, further comprising: a second 2D material electrode bonding layer connected to a second end of the channel, the second 2D material electrode bonding layer being spaced apart from the gate electrode and the source electrode; and a second stressor on at least one of the insulating layer and the drain electrode, the second stressor adjacent to the second 2D material electrode bonding layer and configured to apply a tensile strain to the second 2D material electrode bonding layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects, features, and advantages of certain embodiments of the disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0031] FIG. 1 illustrates a structure of a stressor of a field effect transistor before a chemical reaction, according to an example embodiment;

[0032] FIG. 2 illustrates a structure of a stressor of a field effect transistor after a chemical reaction, according to an example embodiment;

[0033] FIG. 3 illustrates an example in which an interlayer is further provided in the field effect transistor of FIG. 2;

[0034] FIGS. 4, 5, and 6 illustrate a field effect transistor according to another example embodiment;

[0035] FIGS. 7 and 8 illustrate a field effect transistor according to another example embodiment;

[0036] FIGS. 9 and 10 illustrate a field effect transistor according to another example embodiment;

[0037] FIGS. 11 and 12 illustrate a field effect transistor according to another example embodiment;

[0038] FIG. 13 is a diagram of a method of manufacturing a field effect transistor according to an example embodiment;

[0039] FIG. 14 illustrates a volume change according to an oxidation reaction of a stressor according to an example embodiment;

[0040] FIG. 15 illustrates a comparative example in which no strain is applied to a two-dimensional (2D) material electrode bonding layer;

[0041] FIG. 16A illustrates an example in which a field effect transistor has a top gate structure according to an example embodiment;

[0042] FIG. 16B illustrates an example in which a field effect transistor has a double-gate structure according to an example embodiment;

[0043] FIG. 16C illustrates an example of a memory structure including a field effect transistor according to an example embodiment;

[0044] FIG. 17 is a schematic block diagram of a display driver integrated circuit (IC) (DDI) including a field effect transistor according to an example embodiment, and a display device including the DDI;

[0045] FIG. 18 is a circuit diagram of a complementary metal-oxide semiconductor (CMOS) inverter including a field effect transistor according to an example embodiment;

[0046] FIG. 19 is a circuit diagram of a CMOS static random-access memory (SRAM) device including a field effect transistor according to an example embodiment;

[0047] FIG. 20 is a circuit diagram of a CMOS NAND circuit including a field effect transistor according to an example embodiment;

[0048] FIG. 21 is a block diagram of an electronic apparatus including a field effect transistor according to an example embodiment; and

[0049] FIG. 22 is a block diagram of an electronic apparatus including a field effect transistor according to an example embodiment.

DETAILED DESCRIPTION

[0050] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are merely described below, by referring to the figures, to explain aspects. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, “at least one of A, B, and C,” and similar language (e.g., “at least one selected from the group consisting of A, B, and C”) may be construed as A only, B only, C only, or any combination of two or more of A, B, and C, such as, for instance, ABC, AB, BC, and AC.

[0051] Hereinafter, a field effect transistor, an electronic apparatus including the same, and a method of manufacturing the field effect transistor according to various embodiments will be described in detail with reference to the accompanying drawings. In the following drawings, like reference numerals denote like elements, and the size of each element may be exaggerated for clarity and convenience of description. It will be understood that, although the terms “first”, “second”, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

[0052] An expression used in the singular form also encompasses the plural expression unless it has a clearly different meaning in the context. It will be further understood that when a part “includes” or “comprises” an element, the part may further include other elements, not excluding the other elements, unless defined otherwise. Also, in the drawings, the size or thickness of each element may be exaggerated for clarity of description. It will be further understood that when a material layer is referred to as being “on” another substrate or layer, the material layer may be directly on the other substrate or layer, or a third layers may be present therebetween. Also, materials constituting each layer in the following embodiments are exemplary, and other materials than the described ones may also be used.

[0053] Also, the terms “ . . . unit,” “module,” etc. used in the specification indicate a unit that processes at least one function or motion, and the unit may be implemented by hardware or software, or by a combination of hardware and software.

[0054] The particular implementations shown and described herein are examples of the present disclosure and are not intended to otherwise limit the scope of the present disclosure in any way. For brevity of the specification, descriptions of conventional electronic configurations, control systems, software, and other functional aspects of the systems may be omitted. Also, line connections or connection members between elements depicted in the drawings represent functional connections and/or physical or circuit connections by way of example, and in an actual device, they may be replaced or embodied with various suitable additional functional connections, physical connections, or circuit connections.

[0055] The use of term “the” and other similar determiners may correspond to both a singular form and a plural form.

[0056] Unless orders of operations included in a method are specifically described, the operations may be performed according to appropriate orders. Also, the use of all example terms (e.g., “such as” and “etc.”) is intended merely to describe the disclosure in detail and does not pose a limitation on the scope of the disclosure unless otherwise claimed.

[0057] FIG. 1 is a cross-sectional view of a field effect transistor according to an example embodiment.

[0058] A field effect transistor 100 includes a substrate 110, a gate electrode 120 provided on the substrate 110, an insulating layer 125 provided on the gate electrode 120, a source electrode 131 provided on the insulating layer 125, a drain electrode 132 provided apart from the source electrode 131, and a channel 135 provided between the source electrode 131 and the drain electrode 132.

[0059] The substrate 110 may be an insulating substrate, or may be a semiconductor substrate having an insulating layer formed on a surface thereof. The semiconductor substrate may include, for example, Si, Ge, SiGe, or a Group III-V semiconductor material. The substrate 110 may be, for example, a silicon substrate having silicon oxide formed on a surface thereof, but is not limited thereto.

[0060] The channel 135 may include a two-dimensional (2D) material. The 2D material may include graphene, black phosphorus, phosphorene, or transition metal dichalcogenide. The transition metal dichalcogenide may include one transition metal selected from the group consisting of Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, Cu, Ga, In, Sn, Ge, and Pb and chalcogen elements selected from the group consisting of S, Se, and Te. The transition metal dichalcogenide may include, for example, one of MoS.sub.2, WS.sub.2, MoSe.sub.2, and WSe.sub.2.

[0061] A first 2D material electrode bonding layer 136 may be provided adjacent to the source electrode 131, and a second 2D material electrode bonding layer 137 may be provided adjacent to the drain electrode 132. The first 2D material electrode bonding layer 136 may be arranged to face the source electrode 131, and may be arranged in direct contact with the source electrode 131. The second 2D material electrode bonding layer 137 may be arranged to face the drain electrode 132, and may be arranged in direct contact with the source electrode 132. The first 2D material electrode bonding layer 136 and the second 2D material electrode bonding layer 137 include a 2D material, wherein the 2D material is the same as described above. The first 2D material electrode bonding layer 136 and the second 2D material electrode bonding layer 137 may extend from the channel 135. A first stressor 141 may be provided on the first 2D material electrode bonding layer 136, and a second stressor 142 may be provided on the second 2D material electrode bonding layer 137. Positions of the first stressor 141 and the second stressor 142 are not limited thereto, and the first and second stressors 141 and 142 may be respectively positioned above or below the first and second 2D material electrode bonding layers 136 and 137, or below the source and drain electrodes 131 and 132. The first and second stressors 141 and 142 may include, for example, a material represented by (M1).sub.a(M2).sub.b, wherein M1 may include any one of Mo, W, Hf, Nb, and Si, M2 may include any one of O, S, Se, Te, and N, and 0<a≤3 and 0<b≤3. The first and second stressors 141 and 142 may include chemical reactants of M1 and M2. FIG. 1 illustrates a state in which the first 2D material electrode bonding layer 136 and the second 2D material electrode bonding layer 137 are in a strain-free state.

[0062] Referring to FIG. 2, a chemical reaction may occur in each of first and second stressors 141a and 142a, and volumes of the first and second stressors 141a and 142a may increase according to the chemical reactions of the first and second stressors 141a and 142a. When the volumes of the first and second stressors 141a and 142a increase, a first 2D material-electrode bonding layer 136a and a second 2D material electrode bonding layer 137a may be stretched, and thus, the first 2D material electrode bonding layer 136a and the second 2D material-electrode bonding layer 137a may include a tensile strain region.

[0063] Because the first and second stressors 141a and 142a are provided on the first 2D material electrode bonding layer 136a and the second 2D material electrode bonding layer 137a, and not on the channel 135, the channel 135 may be configured to have no strain region. When a strain is applied to the channel 135, because the channel 135 has a large energy bandgap, off-current may increase. Accordingly, no strain is applied to the channel 135.

[0064] Meanwhile, as illustrated in FIG. 3, an interlayer 138 may be further provided between the first material electrode bonding layer 136a and the first stressor 141a and between the second material electrode bonding layer 137a and the second stressor 142a. The interlayer 138 may include TiOx (0<x≤3) or CrOx (0<x≤3). The interlayer 138 may increase a bonding force between the first and second 2D material electrode bonding layers 136a and 137a and the first and second stressors 141a and 142a.

[0065] FIGS. 4, 5, and 6 illustrate an example in which a position of a stressor is changed. In FIG. 4, elements using the same reference numerals as those in FIG. 1 perform substantially the same functions and operations, and thus, detailed descriptions thereof are omitted. The first stressor 141a and the second stressor 142a may be provided on the insulating layer 125, the second stressor being arranged apart from the first stressor 141a. Referring to FIG. 5, the channel 135 may be provided in a region facing the gate electrode 120, the first 2D material electrode bonding layer 136a may be provided on the first stressor 141a, and the second 2D material electrode bonding layer 137a may be provided on the second stressor 142a. When the first stressor 141a and the second stressor 142a are chemically reacted, for example, oxidized, the first 2D material electrode bonding layer 136a and the second 2D material electrode bonding layer 137a may include a tensile strain region. The channel 135 has no strain region. Referring to FIG. 6, the source electrode 131 may be provided on the first 2D material electrode bonding layer 136a, and the drain electrode 132 may be provided on the second 2D material electrode bonding layer 137a. The first stressor 141a and the second stressor 142a may be provided adjacent to the first 2D material electrode bonding layer 136a and the second 2D material electrode bonding layer 137a, respectively, and may be arranged not to contact the channel 135.

[0066] In FIG. 7, as compared with FIG. 6, positions of the source electrode 131 and the first 2D material electrode bonding layer 136 are switched, and positions of the drain electrode 132 and the second 2D material electrode bonding layer 137 are switched. The first stressor 141 and the second stressor 142 may arranged apart from each other on the insulating layer 125, and the channel 135 may be provided between the first stressor 141 and the second stressor 142. The source electrode 131 may be provided on the first stressor 141, and the drain electrode 132 may be provided on the second stressor 142. The first 2D material electrode bonding layer 136 may be provided on the source electrode 131, and the second 2D material electrode bonding layer 137 may be provided on the drain electrode 132.

[0067] Referring to FIG. 8, the first stressor 141a and the second stressor 142a may be oxidized, and according to volume changes of the first stressor 141a and the second stressor 142a, the first 2D material electrode bonding layer 136a and the second 2D material electrode bonding layer 137a may include a tensile strain region.

[0068] Referring to FIG. 9, the first stressor 141 may be provided between a side portion of the source electrode 131 and the first 2D material electrode bonding layer 136, and the second stressor 142 may be provided between a side portion of the drain electrode 132 and the second 2D material electrode bonding layer 137. Referring to FIG. 10, the first stressor 141a and the second stressor 142a may be oxidized so that the volumes thereof may increase, and according to the volume changes of the first stressor 141a and the second stressor 142a, the first 2D material electrode bonding layer 136a and the second 2D material electrode bonding layer 137a may include a tensile strain region. In this case, the first 2D material electrode bonding layer 136a on an upper portion of the source electrode 131 and the second 2D material electrode bonding layer 137a on an upper portion of the drain electrode 131 may not include a strain region.

[0069] Referring to FIG. 11, the first stressor 141 may be provided between the upper portion of the source electrode 131 and the first 2D material electrode bonding layer 136, and the second stressor 142 may be provided between the upper portion of the drain electrode 132 and the second 2D material electrode bonding layer 137. Referring to FIG. 12, the first stressor 141a and the second stressor 142a may be oxidized so that the volumes thereof may increase, and according to the volume changes of the first stressor 141a and the second stressor 142a, the first 2D material electrode bonding layer 136a and the second 2D material electrode bonding layer 137a may include a tensile strain region. In the first 2D material electrode bonding layer 136a and the second 2D material electrode bonding layer 137b, a strain region may be locally provided in a region in contact with the first stressor 141a and the second stressor 142a.

[0070] FIG. 13 is a diagram of a method of manufacturing a field effect transistor according to an example embodiment. The method of manufacturing a field effect transistor will be described with reference to FIGS. 1 and 2.

[0071] The method of manufacturing a field effect transistor according to an example embodiment includes forming the gate electrode 125 on the substrate 110 (S10), forming the insulating layer 125 on the gate electrode 125 (S20), and forming the source electrode 131 and the drain electrode 132 on the insulating layer 125 (S30). Also, the channel 135 may be formed between the source electrode 131 and the drain electrode 132 (S40). A 2D material electrode bonding layer may be formed adjacent to the source electrode 131 and the drain electrode 132 (S50). The first 2D material electrode bonding layer 136 may be formed adjacent to the source electrode 131, and the second 2D material electrode bonding layer 137 may be formed adjacent to the drain electrode 132. The first 2D material electrode bonding layer 136 may be provided in direct contact with the source electrode 131, and the second 2D material electrode bonding layer 137 may be provided in direct contact with the drain electrode 132. However, the present disclosure is not limited thereto, and the first 2D material electrode bonding layer 136 may be provided adjacent to the source electrode 131 without being in direct contact with the source electrode 131, and the second 2D material electrode bonding layer 137 may be provided adjacent to the drain electrode 132 without being in direct contact with the drain electrode 132.

[0072] The first 2D material electrode bonding layer 136 and the second 2D material electrode bonding layer 137 may extend from the channel 135 to be integrally formed.

[0073] Next, a stressor may be formed (S60). The stressor may include a chemically reactive material. The order of forming the stressor may vary depending on a position of the stressor. In FIG. 1, the first stressor 141 may be formed on an upper portion of the first 2D material electrode bonding layer 136, the second stressor 142 may be formed on an upper portion of the second 2D material electrode bonding layer 137.

[0074] A tensile strain may be applied to the 2D material electrode bonding layer by chemically reacting a stressor (S70). When the stressor is chemically reacted, for example, a MoS.sub.2 stressor may be reacted at a temperature of about 330° C. in an oxygen or chalcogen atmosphere to induce volume expansion of the stressor. Referring to FIG. 2, the first stressor 141 may be oxidized, and the first stressor 141a that has been oxidized may have an increased volume. The second stressor 142 may be oxidized, and the second stressor 142a that has been oxidized may have an increased volume. A tensile strain region may be formed in a first 2D material electrode bonding layer 136a by the first stressor 141a that has been oxidized, and a tensile strain region may be formed in the second 2D material electrode bonding layer 137a by the second stressor 142a that has been oxidized.

[0075] In the method of manufacturing a field effect transistor according to an example embodiment, a stressor may be formed adjacent to a 2D material electrode bonding layer, and a tensile strain may be applied locally to the 2D material electrode bonding layer by oxidizing the stressor. A region to which the tensile strain is applied in the 2D material electrode bonding layer may be selectively controlled according to a position of the stressor and an area of the stressor. FIG. 14 illustrates that when a Cr layer is deposited on an Au layer (L.sub.0=10 nm), and the Cr layer is oxidized, a thickness of the oxidized Cr.sub.2O.sub.3 is increased by about 40 nm (ΔL). The greater the chemical reaction of the stressor, the greater the volume change of the stressor, and the greater the size of the strain applied to the 2D material electrode bonding layer. For example, when a volume of the 2D material electrode bonding layer is doubled, strain (ε)=25.99%. More specifically, assuming that a thickness of the Cr layer is L before the reaction and expands isotropically after the reaction, in order for the volume of the Cr layer to be doubled after the reaction, the thickness of the Cr layer is changed to 2.sup.1/3 L. In this case, strain (ε)=(ΔL/LO)*100=(2.sup.1/3 L−L)/L*100(%)=25.99%.

[0076] The size of the strain may be controlled by controlling the volume change of the stressor according to the degree of chemical reaction of the stressor. When a tensile strain is applied to the 2D material electrode bonding layer, an effective mass may decrease and carrier density may increase, thereby improving mobility. Accordingly, in the method of manufacturing a field effect transistor according to an example embodiment, a tensile strain is selectively applied to a 2D material electrode bonding layer such that the contact resistance of the 2D material electrode bonding layer may decrease, thereby increasing the conductivity thereof, while no strain is applied to a channel such that an increase in off current in the channel due to strain application may be prevented.

[0077] The field effect transistor according to an example embodiment may be applied to various 2D-based devices, and may contribute to improving characteristics of the 2D-based devices by improving the conductivity of a 2D material electrode bonding layer. The field effect transistor according to an example embodiment may be applied to, for example, a logic transistor, a memory selector transistor, a three-dimensional (3D) monolithic transistor, etc. When a strain is applied to a 2D material, the band structure, bandgap, conductivity, and effective mass thereof may increase or decrease according to the strain type, and thus, the conductivity of the material may be controlled.

[0078] When a tensile strain is applied to an n-type channel such as MoS.sub.2, electron mobility may increase, mobility may be improved by about 9%, and an energy bandgap may decrease. Also, resistance may decrease when the tensile strain is applied. Accordingly, carrier injection may be improved by applying the tensile strain to the 2D material electrode bonding layer, as compared with an unstrained 2D-based field effect transistor.

[0079] FIG. 15 illustrates a comparative example. The comparative example is a 2D-based field effect transistor in which no strain is applied to both a channel and a 2D material electrode bonding layer. In the comparative example, an Au/In electrode structure maintains a non-oxidized state.

[0080] The size and type of a strain applied to a 2D material may be confirmed through Raman and photoluminescence (PL). When a tensile strain occurs, changes in a Raman peak down shift and peak splitting (in the case of MoS.sub.2, an E.sub.2g.sup.1 peak is a measure) may appear, and a PL peak position and intensity may decrease. In the case of a compressive strain, opposite Raman and PL changes may appear. No strain occurs in the field effect transistor of the comparative example.

[0081] FIG. 16A illustrates an example in which a field effect transistor 200 according to an example embodiment is applied to a top gate structure.

[0082] The field effect transistor 200 includes a substrate 210, a source electrode 221 provided on the substrate 210, a drain electrode 222 provided apart from the source electrode 221 on the substrate 210, and a channel 225 provided between the source electrode 221 and the drain electrode 222. A first 2D material electrode bonding layer 231a may be provided on the source electrode 221, and a second 2D material electrode bonding layer 232a may be provided on the drain electrode 222. The first 2D material electrode bonding layer 231a and the second 2D material electrode bonding layer 232a may include a tensile strain region. A first stressor 241a may be provided on the first 2D material electrode bonding layer 231a, and a second stressor 242a may be provided on the second 2D material electrode bonding layer 232a. The first stressor 241a and the second stressor 242a may include a material represented by (M1)a(M2)b, wherein M1 may include any one of Mo, W, Hf, Nb, and Si, M2 may include O, S, Se, Te, and N, and 0<a≤3 and 0<b≤3. The first stressor 241a and the second stressor 242a may have an oxidation reaction, nitridation reaction, or chalcogenide reaction structure.

[0083] An insulating layer 250 may be provided to cover the first stressor 241a, the second stressor 242a, and the channel 225, and a gate electrode 260 may be provided on the insulating layer 250. The gate electrode 260 may be provided inside the insulating layer 250 or on the insulating layer 250. In the present embodiment, the field effect transistor 200 may be applied in substantially the same manner as the field effect transistor having a bottom gate structure described with reference to FIGS. 1 to 12, except for having a top gate structure.

[0084] Additionally, in an example embodiment, a field effect transistor may have a double-gate structure. FIG. 16B illustrates an example in which a field effect transistor has a double-gate structure according to an example embodiment.

[0085] Referring to FIG. 16B, a field effect transistor 300 may have the same structure as the field effect transistor 100 described in FIG. 1, except the field effect transistor 300 may further include an insulating layer 125′ covering the first stressor 141, channel 135, and second stressor 142, and a gate electrode 120′ on the insulating layer 125′ over the channel 135. The materials for the insulating layer 125 and 125′ are not particularly limited and may be formed of any one of various materials suitable for gate insulating layers in transistors, such as silicon oxide, a high-k dielectric (e.g., aluminum oxide, hafnium oxide), and the like. The field effect transistor 300 may have a double-gate structure, in a which a bottom gate 120 and a top-gate 120′ are provided.

[0086] While FIG. 16B is an example in which the transistor 100 in FIG. 1 further includes the insulating layer 125′ and gate electrode 120′, the transistors 100 described in FIGS. 2 to 12 also may be modified to have a double-gate structure by forming an insulating layer 125′ over the bottom-gate transistor and forming a gate electrode 120′ on the insulating layer 125′ over the channel 135.

[0087] The field effect transistor according to an example embodiment has a highly miniaturized size and exhibits excellent electrical performance, and thus is suitable for an integrated circuit (IC) device having a high degree of integration. The field effect transistor according to an example embodiment may constitute a transistor constituting a digital circuit or an analog circuit. In some embodiments, the field effect transistor may be used as a high-voltage transistor or a low-voltage transistor. For example, the field effect transistor according to an example embodiment may constitute a high-voltage transistor constituting a peripheral circuit of a flash memory device, which is a non-volatile memory device operating at a high voltage, or an electrically erasable and programmable read only memory (ROM) (EEPROM) device. Alternatively, the field effect transistor according to an example embodiment may constitute a transistor included in an IC device for a liquid crystal display (LCD) requiring an operating voltage of 10 V or more, for example, an operating voltage of about 20 V to about 30 V, or an IC chip used in a plasma display panel (PDP) requiring an operating voltage of about 100 V.

[0088] FIG. 16C illustrates an example of a memory structure including a field effect transistor according to an example embodiment.

[0089] Referring to FIG. 16C, the memory structure 400 may be the same as the transistor 100 in FIG. 1, except the memory structure 400 may further include a data storage element DS connected to the drain electrode 132 through a plug P to provide a memory structure. The plug P may include a conductive material such as a metal or metal alloy and may penetrate through an interlayer dielectric ILD to electrically contact the drain electrode 132. The plug P may also penetrate through layers between the drain electrode 132 and the data storage element DS. For example, as shown in FIG. 16C. the plug P penetrates through the second stressor 142 and the second 2D material electrode bonding layer 137. The data storage element DS may be capable of storing data corresponding to ‘1’ or ‘0.’ The data storage element DS may be a capacitor or a magnetic tunnel junction, but is not limited thereto.

[0090] While FIG. 16C illustrates an example of a memory structure 400 in which the transistor 100 in FIG. 1 further includes interlayer dielectric ILD, plug P, and data storage DS to provide the memory structure 400, the transistors 100 described in FIGS. 2 to 12 and transistors 200 and 300 in FIGS. 16A and 16B also may be modified similarly to provide a memory structure including the interlayer dielectric ILD, plug P, and data storage DS.

[0091] FIG. 17 is a schematic block diagram of a display driver IC (DDI) 500 according to an example embodiment, and a display device 520 including the DDI 500.

[0092] Referring to FIG. 17, the DDI 500 may include a controller 502, a power supply circuit 504, a driver block 506, and a memory block 508. The controller 502 receives and decodes a command applied from a main processing unit (MPU) 522, and controls each block of the DDI 500 to implement an operation according to the command. The power supply circuit 504 generates a driving voltage in response to the control by the controller 502. The driver block 506 drives a display panel 524 by using the driving voltage generated by the power supply circuit 504 in response to the control by the controller 502. The display panel 524 may be a liquid crystal display panel or a plasma display panel. The memory block 508 may be a block for temporarily storing commands input to the controller 502 or control signals output from the controller 502, or for storing necessary data, and may include memory such as random access memory (RAM) or ROM. The power supply circuit 504 and the driver block 506 may include the field effect transistor according to an example embodiment described above with reference to FIGS. 1 to 15.

[0093] FIG. 18 is a circuit diagram of a complementary metal-oxide semiconductor (MOS) (CMOS) inverter 600 according to an example embodiment.

[0094] The CMOS inverter 600 includes a CMOS transistor 610. The CMOS transistor 610 includes a p-channel MOS (PMOS) transistor 620 and an n-channel MOS (NMOS) transistor 630 connected between a power terminal Vdd and a ground terminal. The CMOS transistor 610 may include the field effect transistor according to an example embodiment described above with reference to FIGS. 1 to 16.

[0095] FIG. 19 is a circuit diagram of a CMOS static RAM (SRAM) device 700 according to an example embodiment.

[0096] The CMOS SRAM device 700 includes a pair of driving transistors 710. Each of the pair of driving transistors 710 includes a PMOS transistor 720 and an NMOS transistor 730 connected between a power terminal Vdd and a ground terminal. The CMOS SRAM device 700 may further include a pair of transfer transistors 740. A source of the transfer transistor 740 is cross-connected to a common node of the PMOS transistor 720 and the NMOS transistor 730 constituting the driving transistor 710. The power terminal Vdd is connected to the source of the PMOS transistor 720, and the ground terminal is connected to the source of the NMOS transistor 730. A word line WL may be connected to gates of the pair of transfer transistors 740, and a bit line BL and an inverted bit line may be respectively connected to drains of the pair of transfer transistors 740.

[0097] At least one of the driving transistor 710 and the transfer transistor 740 of the CMOS SRAM device 700 may include the field effect transistor according to an example embodiment described above with reference to FIGS. 1 to 16.

[0098] FIG. 20 is a circuit diagram of a CMOS NAND circuit 800 according to an example embodiment.

[0099] The CMOS NAND circuit 800 includes a pair of CMOS transistors to which different input signals are transmitted. The CMOS NAND circuit 800 may include the field effect transistor according to an example embodiment described above with reference to FIGS. 1 to 16.

[0100] FIG. 21 is a block diagram of an electronic apparatus 900 according to an example embodiment.

[0101] The electronic apparatus 900 includes a memory 910 and a memory controller 920. The memory controller 920 may control the memory 910 to read data from the memory 910 and/or to write data to the memory 910 in response to a request of a host 930. At least one of the memory 910 and the memory controller 920 may include the field effect transistor according to an example embodiment described above with reference to FIGS. 1 to 16.

[0102] FIG. 22 is a block diagram of an electronic apparatus 1000 according to an example embodiment.

[0103] The electronic apparatus 1000 may constitute a wireless communication device, or a device capable of transmitting and/or receiving information in a wireless environment. The electronic apparatus 1000 includes a controller 1010, an input/output (I/O) device 1020, a memory 1030, and a wireless interface 1040, which are interconnected through a bus 1050.

[0104] The controller 1010 may include at least one of a microprocessor, a digital signal processor, or a processing device similar thereto. The I/O device 1020 may include at least one of a keypad, a keyboard, or a display. The memory 1030 may be used to store commands executed by the controller 1010. For example, the memory 1030 may be used to store user data. The electronic apparatus 1000 may use the wireless interface 1040 to transmit/receive data through a wireless communication network. The wireless interface 1040 may include an antenna and/or a wireless transceiver. In some embodiments, the electronic apparatus 1000 may be used for a third generation communication system, for example, code division multiple access (CDMA), global system for mobile communications (GSM), north American digital cellular (NADC), extended-time division multiple access (E-TDMA), and/or a communication interface protocol for the third generation communication system, for example, wide band code division multiple access (WCDMA). The electronic apparatus 1000 may include the field effect transistor according to an example embodiment described above with reference to FIGS. 1 to 16.

[0105] The field effect transistor according to an example embodiment may exhibit good electrical performance with a highly miniaturized structure, and thus may be applied to an IC device, and may realize miniaturization, low power, and high performance.

[0106] In the field effect transistor according to an example embodiment, the conductivity of a 2D material electrode bonding layer may be increased by applying a tensile strain to the 2D material electrode bonding layer via a stressor. The electronic apparatus according to an example embodiment may be miniaturized and improved in electrical performance by including the field effect transistor. In the method of manufacturing a field effect transistor according to an example embodiment, a tensile strain may be applied to a 2D material electrode bonding layer by oxidizing a stressor to increase a volume thereof.

[0107] One or more of the elements disclosed above may include or be implemented in processing circuitry such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry more specifically may include, but is not limited to, a central processing unit (CPU) , an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc.

[0108] It should be understood that embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims.