Patent classifications
H01L21/02549
Semiconductor device and fabrication method
A semiconductor device comprising a silicon substrate on which is grown a <100 nm thick epilayer of AlAs or related compound, followed by a compound semiconductor other than GaN buffer layer. Further III-V compound semiconductor structures can be epitaxially grown on top. The AlAs epilayer reduces the formation and propagation of defects from the interface with the silicon, and so can improve the performance of an active structure grown on top.
USE OF AT LEAST ONE BINARY GROUP 15 ELEMENT COMPOUND, A 13/15 SEMICONDUCTOR LAYER AND BINARY GROUP 15 ELEMENT COMPOUNDS
The invention provides the use of at least one binary group 15 element compound of the general formula R.sup.1R.sup.2E-E′R.sup.3R.sup.4 (I) or R.sup.5E(E′R.sup.6R.sup.7)2 (II) as the educt in a vapor deposition process. In this case, R.sup.1, R.sup.2, R.sup.3 and R.sup.4 are independently selected from the group consisting of H, an alkyl radical (C1-C10) and an aryl group, and E and E′ are independently selected from the group consisting of N, P, As, Sb and Bi. This use excludes hydrazine and its derivatives. The binary group 15 element compounds according to the invention allow the realization of a reproducible production and/or deposition of multinary, homogeneous and ultrapure 13/15 semiconductors of a defined combination at relatively low process temperatures. This makes it possible to completely waive the use of an organically substituted nitrogen compound such as 1.1 dimethyl hydrazine as the nitrogen source, which drastically reduces nitrogen contaminations—compared to the 13/15 semiconductors and/or 13/15 semiconductor layers produced with the known production methods.
AlInAsSb Avalanche Photodiode and Related Method thereof
An avalanche photodiode, and related method of manufacture and method of use thereof, that includes a first contact layer; a multiplication layer, wherein the multiplication layer includes AlInAsSb; a charge, wherein the charge layer includes AlInAsSb; an absorption, wherein the absorption layer includes AlInAsSb; a blocking layer; and a second contact layer.
Semiconductor structure and method for manufacturing thereof
A semiconductor structure and method for manufacturing thereof are provided. The semiconductor structure includes a silicon substrate having a first surface, a III-V layer on the first surface of the silicon substrate and over a first active region, and an isolation region in a portion of the III-V layer extended beyond the first active region. The first active region is in proximal to the first surface. The method includes the following operations. A silicon substrate having a first device region and a second device region is provided, a first active region is defined in the first device region, a III-V layer is formed on the silicon substrate, an isolation region is defined across a material interface in the III-V layer by an implantation operation, and an interconnect penetrating through the isolation region is formed.
Infrared detection element
This infrared detection element includes a buffer layer (InAsSb layer) 3, a buffer layer (InAs layer) 4, and a light absorption layer (InAsSb layer) 5. A critical film thickness hc of the InAs layer satisfies a relation of hc<t with a thickness t of the InAs layer. In this case, it is possible to improve crystallinities of the buffer layer 4 of InAs and the light absorption layer 5 of InAsSb formed on the buffer layer 3.
SAG NANOWIRE GROWTH WITH A PLANARIZATION PROCESS
The present disclosure relates to a method of manufacturing a nanowire structure. According to an exemplary process, a substrate is firstly provided. An intact buffer region is formed over the substrate, and a sacrificial top portion of the intact buffer region is eliminated to provide a buffer layer with a planarized top surface. Herein, the planarized top surface has a vertical roughness below 10 Å. Next, a patterned mask with an opening is formed over the buffer layer, such that a portion of the planarized top surface of the buffer layer is exposed. A nanowire is formed over the exposed portion of the planarized top surface of the buffer layer through the opening of the patterned mask. The buffer layer is configured to have a lattice constant that provides a transition between the lattice constant of the substrate and the lattice constant of the nanowire.
Method for growing III-V compound semiconductor thin films on silicon-on-insulators
The present disclosure relates to a method for growing III-V compound semiconductors on silicon-on-insulators. Starting from {111}-oriented Si seed surfaces between a buried oxide layer and a patterned mask layer, the III-V compound semiconductor is grown within lateral trenches by metal organic chemical vapor deposition such that the non-defective portion of the III-V compound semiconductor formed on the buried oxide layer is substantially free of crystalline defects and has high crystalline quality.
Methods for depositing III-alloys on substrates and compositions therefrom
A method for depositing III-V alloys on substrates and compositions therefrom. A first layer comprises a Group III element. A second layer comprises a silica. A substrate has a surface. The second layer is deposited onto a first layer. The depositing is performed by a sol-gel method. The second layer is exposed to a precursor that comprises a Group V element. At least one of the precursor or the Group V element diffuse through the silica. The first layer is transformed into a solid layer comprising a III-V alloy, wherein at least a portion of the first layer to a liquid. The silica retains the liquified first layer, enabling at least one of the precursor or the Group V element to diffuse into the liquid, resulting in the forming of the III-V alloy.
Optimized heteroepitaxial growth of semiconductors
A method of performing HVPE heteroepitaxy comprises exposing a substrate to a carrier gas, a first precursor gas, a Group II/III element, and ternary-forming gasses (V/VI group precursor), to form a heteroepitaxial growth of a binary, ternary, and/or quaternary compound on the substrate; wherein the carrier gas is H.sub.2, wherein the first precursor gas is HCl, the Group II/III element comprises at least one of Zn, Cd, Hg, Al, Ga, and In; and wherein the ternary-forming gasses comprise at least two or more of AsH.sub.3 (arsine), PH.sub.3 (phosphine), H.sub.2Se (hydrogen selenide), H.sub.2Te (hydrogen telluride), SbH.sub.3 (hydrogen antimonide, or antimony tri-hydride, or stibine), H.sub.2S (hydrogen sulfide), NH.sub.3 (ammonia), and HF (hydrogen fluoride); flowing the carrier gas over the Group II/III element; exposing the substrate to the ternary-forming gasses in a predetermined ratio of first ternary-forming gas to second ternary-forming gas (1tf:2tf ratio); and changing the 1tf:2tf ratio over time.
Optimized thick heteroepitaxial growth of semiconductors with in-situ substrate pretreatment
A method of performing HVPE heteroepitaxy comprises exposing a substrate to a carrier gas, a first precursor gas, a Group II/III element, and ternary-forming gasses (V/VI group precursor), to form a heteroepitaxial growth of a binary, ternary, and/or quaternary compound on the substrate; wherein the carrier gas is Hz, wherein the first precursor gas is HCl, the Group II/III element comprises at least one of Zn, Cd, Hg, Al, Ga, and In; and wherein the ternary-forming gasses comprise at least two or more of AsH.sub.3 (arsine), PH.sub.3 (phosphine), H.sub.2Se (hydrogen selenide), HzTe (hydrogen telluride), SbH.sub.3 (hydrogen antimonide, or antimony tri-hydride, or stibine), H.sub.2S (hydrogen sulfide), NH.sub.3 (ammonia), and HF (hydrogen fluoride); flowing the carrier gas over the Group II/III element; exposing the substrate to the ternary-forming gasses in a predetermined ratio of first ternary-forming gas to second ternary-forming gas (1tf:2tf ratio); and changing the 1tf:2tf ratio over time.