The present disclosure provides a manufacturing method of a complementary metal-oxide-semiconductor (CMOS) inverter includes annealing a substrate printed with an oxide ink to obtain a first active layer, printing a carbon tube ink between a first source and the first drain to form a second active layer for obtaining a first thin-film transistor (TFT), forming a second source and a second drain on two sides of the first active layer to obtain a second TFT, and forming wires between the first TFT and the second TFT.

A transistor including a channel layer including an oxide semiconductor material and methods of making the same. The transistor includes a channel layer having a first oxide semiconductor layer having a first oxygen concentration, a second oxide semiconductor layer having a second oxygen concentration and a third oxide semiconductor layer having a third oxygen concentration. The second oxide semiconductor layer is located between the first semiconductor oxide layer and the third oxide semiconductor layer. The second oxygen concentration is lower than the first oxygen concentration and the third oxygen concentration.

Metal oxide nanostructure and methods of making metal oxide nanostructures are provided. The metal oxide nanostructures can be 1-dimensional nanostructures such as nanowires, nanofibers, or nanotubes. The metal oxide nanostructures can be doped or un-doped metal oxides. The metal oxide nanostructures can be deposited onto a variety of substrates. The deposition can be performed without high pressures and without the need for seed catalysts on the substrate. The deposition can be performed by laser ablation of a target including a metal oxide and, optionally, a dopant. In some embodiments zinc oxide nanostructures are deposited onto a substrate by pulsed laser deposition of a zinc oxide target using an excimer laser emitting UV radiation. The zinc oxide nanostructure can be doped with a rare earth metal such as gadolinium. The metal oxide nanostructures can be used in many devices including light-emitting diodes and solar cells.

A semiconductor device with high reliability is provided. A first step of forming a metal oxide containing indium over a substrate and a second step of performing microwave treatment from above the metal oxide are included. The first step is performed by a sputtering method using an oxide target containing indium. The second step is performed using a gas containing oxygen under reduced pressure, and by the second step, a defect in which hydrogen has entered an oxygen vacancy (VoH) in the metal oxide is divided into an oxygen vacancy (Vo) and hydrogen (H).

A semiconductor device includes a monocrystalline substrate configured to form a channel region between two recesses in the substrate. A gate conductor is formed on a passivation layer over the channel region. Dielectric pads are formed in a bottom of the recesses and configured to prevent leakage to the substrate. Source and drain regions are formed in the recesses on the dielectric pads from a deposited non-crystalline n-type material with the source and drain regions making contact with the channel region.

A semiconductor device with high reliability is provided by the following steps: forming an oxide semiconductor; forming a first insulator in contact with the oxide semiconductor; forming a second insulator over the first insulator, forming a third insulator over the second insulator; forming an opening in the third insulator, the second insulator, and the first insulator, cleaning the inside of the opening; embedding a conductor in the cleaned opening; forming the first insulator to include an excess-oxygen region; forming the second insulator to have a higher barrier property against oxygen, hydrogen, or water than the first insulator, and processing the opening to have a cylindrical shape or an inverted cone shape.

A sputtering equipment configured to grow a gallium oxide film on a substrate is proposed, and the sputtering equipment may include: a chamber; a stage located in the chamber and configured to secure the substrate thereon; a gallium target located in the chamber and including gallium elements; a first power supply configured to apply voltage to the gallium target; and an oxygen element supplier configured to supply oxygen elements into the chamber.

Memory devices and electronic systems include an array of vertical memory cells positioned along respective vertical channels to define vertical memory strings. Each of the vertical channels includes a channel material exhibiting an electron mobility of at least about 30 cm.sup.2/(V.Math.s) and a room temperature band gap of at least about 1.40 eV (e.g., zinc oxide, silicon carbide, indium phosphide, indium gallium zinc oxide, gallium arsenide, or molybdenum disulfide) and a bottom plug material exhibiting a room temperature band gap of less than about 1.10 eV (e.g., silicon germanium, germanium, or indium gallium arsenide). Methods of fabricating a memory device include forming such a bottom plug material within vertical channels and forming such a channel material electrically coupled to the bottom plug material.

A transistor, integrated semiconductor device and methods of making. The transistor includes a patterned gate electrode, a dielectric layer located over the patterned gate electrode and a patterned first oxide semiconductor layer comprising a channel region and source/drain regions located on sides of the channel region. The thickness of the source/drain regions is greater than a thickness of the channel region. The transistor also includes contacts located on the patterned first oxide semiconductor layer and connected to the source/drain regions of the patterned first oxide semiconductor layer.

Disclosed are a crystallization process of an oxide semiconductor, a method of manufacturing a thin film transistor including the same, a thin film transistor, a display panel, and an electronic device. The crystallization process of an oxide semiconductor includes forming an amorphous oxide semiconductor layer on a substrate, forming a crystallization auxiliary layer including a light absorbing inorganic material on the amorphous oxide semiconductor layer, and annealing the crystallization auxiliary layer to crystallize the amorphous oxide semiconductor layer.