A thin layer of lattice matched wide bandgap semiconductor material having semi-insulating properties is employed as an isolation layer between the substrate and a vertical stack of suspended semiconductor channel material nanosheets. The presence of such an isolation layer eliminates the parasitic leakage path between the source region and the drain region that typically occurs through the substrate, while not interfering with the CMOS device that is formed around the semiconductor channel material nanosheets.

A method is provided for preparing semiconductor structure, e.g., a semiconductor on insulator structure, comprising a device layer having a smooth surface. The method provided involves smoothing a semiconductor substrate surface by making use of stress enhanced surface diffusion at elevated temperatures. The purpose of this method is to reach atomic scale surface smoothness (for example, smoothness in the range of between 1.0 and 1.5 angstroms as measured according to root mean square over a 30 um30 um AFM measurement), which is required in advanced (sub 28 nm) CMOS device fabrication.

Provided is a semi-insulating crystal represented by a composition formula In.sub.xAl.sub.yGa.sub.1-x-yN (satisfying 0x1, 0y1, 0x+y1), wherein each concentration of Si, B, and Fe in the crystal is less than 110.sup.15 at/cm.sup.3, electric resistivity under a temperature condition of 20 C. or more and 200 C. or less is 110.sup.6 cm or more.

A terahertz antenna includes at least one photoconductive layer which generates charge carriers upon irradiation of light and two electroconductive antenna elements via which an electric field can be applied to at least one section of the photoconductive layer. The photoconductive layer being doped with a dopant in a concentration of at least 11018 cm3, the dopant being a transition metal. The photoconductive layer is produced by molecular beam epitaxy at a growth temperature of at least 200 C. and not more than 500 C., the dopant being arranged in the photoconductive layer such that it produces a plurality of point defects.

A nitride semiconductor template includes a substrate, and a chlorine-containing nitride semiconductor layer. The chlorine-containing nitride semiconductor layer contains an iron concentration of not higher than 110.sup.17 cm.sup.3.

In a method of manufacturing a semiconductor device, a Schottky electrode is formed on an upper surface of a semiconductor substrate. A second region of the semiconductor substrate is etched such that a first region becomes higher than a second region, a rising surface is formed between the first and second regions, and an outer peripheral edge of the Schottky electrode is located on the first region. An insulating film is formed on the upper surface of the semiconductor substrate such that the insulating film annularly extends along the rising surface. A field plate electrode is formed. The field plate electrode is electrically connected with the Schottky electrode and faces the upper surface of the semiconductor substrate via the insulating film within an area extending from the outer peripheral edge of the Schottky electrode to the second region over the rising surface.

Provided is a technique for manufacturing a nitride semiconductor substrate with which it is possible to manufacture a nitride semiconductor substrate having sufficiently reduced dislocation density with a large area even if manufactured on an inexpensive substrate made of sapphire, etc. A nitride semiconductor substrate in which a nitride semiconductor layer formed on a substrate is formed by laminating an undoped nitride layer and a rare earth element-added nitride layer to which a rare earth element is added as a doping material, and the dislocation density is of the order of 106 cm-2 or less. A method for manufacturing a nitride semiconductor substrate in which a step for growing GaN, InN, AlN, or a mixed crystal of two or more thereof on a substrate to form an undoped nitride layer, and a step for forming a rare earth element-added nitride layer to which a rare earth element is added so as to be substituted for Ga, In, or Al are performed via a series of formation steps using an organic metal vapor epitaxial technique at a temperature of 900 to 1200 C. without extraction from a reaction vessel.

There is provided a semiconductor substrate including: a sapphire substrate; an intermediate layer formed of gallium nitride with random crystal directions and provided on the sapphire substrate; and at least one or more semiconductor layers each of which is formed of a gallium nitride single crystal and that are provided on the intermediate layer.

Provided is an n-type GaN crystal, in which a donor impurity contained at the highest concentration is Ge, and which has a room-temperature resistivity of lower than 0.03 ?.Math.cm and a (004) XRD rocking curve FWHM of less than 20 arcsec. The n-type GaN crystal has two main surfaces, each having an area of 2 cm.sup.2 or larger. One of the two main surfaces can have a Ga polarity and can be inclined at an angle of 0? to 10? with respect to a (0001) crystal plane. Further, the n-type GaN crystal can have a diameter of 20 mm or larger.

A high electron mobility heterostructure and a method of fabricating the heterostructure, wherein the high electron mobility heterostructure comprises a substrate, a buffer on the substrate, a doped charge compensation layer on the buffer, a double continuous grade barrier on the doped charge compensation layer having increasing polarization charge and decreasing polarization charge, a channel on the double continuous grade barrier, and a charge generation layer on the channel. The method comprises forming a substrate, forming a buffer on the substrate, forming a doped charge compensation layer on the buffer, forming a double continuous grade barrier on the doped charge compensation layer, forming a channel on the double continuous grade barrier, and forming a charge generation layer on the channel.