A method includes depositing a semiconductor stack within a first region and a second region on a substrate, the semiconductor stack having alternating layers of a first type of semiconductor material and a second type of semiconductor material. The method further includes removing a portion of the semiconductor stack from the second region to form a trench and with an epitaxial growth process, filling the trench with the second type of semiconductor material. The method further includes patterning the semiconductor stack within the first region to form a nanostructure stack, patterning the second type of semiconductor material within the second region to form a fin structure, and forming a gate structure over both the nanostructure stack and the fin structure.

A static random access memory (SRAM) structure is provided. The structure includes a plurality of SRAM bit cells on a substrate. Each SRAM bit cell includes at least six transistors including at least two NMOS transistors and at least two PMOS transistors. Each of the six transistors is being lateral gate-all-around transistors in that gates wraps all around a cross section of channels of the at least six transistors. The at least six transistors positioned in three decks in which a third deck is positioned vertically above a second deck, and the second deck is positioned vertically above a first deck relative to a working surface of the substrate. A first inverter is formed using a first transistor positioned in the first deck and a second transistor positioned in the second deck. A second inverter is formed using a third transistor positioned in the first deck and a fourth transistor positioned in the second deck. A pass gate is located in the third deck.

A semiconductor device includes a semiconductor fin protruding from a substrate, a gate electrode over the semiconductor fin, a gate insulating layer between the semiconductor fin and the gate electrode, source and drain regions disposed on opposite sides of the semiconductor fin, a first stressor formed in a region between the source and drain regions. The first stressor including one material selected from the group consisting of He, Ne, and Ga.

A method includes removing a first dummy gate structure to form a recess around a first nanostructure and a second nanostructure; depositing a sacrificial layer in the recess with a flowable chemical vapor deposition (CVD); and patterning the sacrificial layer to leave a portion of the sacrificial layer between the first nanostructure and the second nanostructure. The method further include depositing a first work function metal in first recess; removing the first work function metal and the portion of the sacrificial layer from the recess; depositing a second work function metal in the recess, wherein the second work function metal is of an opposite type than the first work function metal; and depositing a fill metal over the second work function metal in the recess.

The present disclosure generally relates to bilayer metal dichalcogenides, to processes for forming bilayer metal dichalcogenides, and to uses of bilayer metal dichalcogenides in devices for quantum electronics. In an aspect, a device is provided. The device includes a gate electrode, a substrate disposed over at least a portion of the gate electrode, and a bottom layer including a first metal dichalcogenide, the bottom layer disposed over at least a portion of the substrate. The device further includes a top layer including a second metal dichalcogenide, the top layer disposed over at least a portion of the bottom layer, the first metal dichalcogenide and the second metal dichalcogenide being the same or different. The device further includes a source electrode and a drain electrode disposed over at least a portion of the top layer.

Devices for photoelectrodes for water splitting based on indium nanowires on flexible substrates as well as methods of manufacture by transferring nanowire arrays to flexible substrates.

The present disclosure describes a method for the formation of gate-all-around nano-sheet FETs with tunable performance. The method includes disposing a first and a second vertical structure with different widths over a substrate, where the first and the second vertical structures have a top portion comprising a multilayer nano-sheet stack with alternating first and second nano-sheet layers. The method also includes disposing a sacrificial gate structure over the top portion of the first and second vertical structures; depositing an isolation layer over the first and second vertical structures so that the isolation layer surrounds a sidewall of the sacrificial gate structure; etching the sacrificial gate structure to expose each multilayer nano-sheet stack from the first and second vertical structures; removing the second nano-sheet layers from each exposed multilayer nano-sheet stack to form suspended first nano-sheet layers; forming a metal gate structure to surround the suspended first nano-sheet layers.

In an embodiment, a method includes: forming a first recess and a second recess in a substrate; growing a first epitaxial material stack in the first recess, the first epitaxial material stack including alternating layers of a first semiconductor material and a second semiconductor material, the layers of the first epitaxial material stack being undoped; growing a second epitaxial material stack in the second recess, the second epitaxial material stack including alternating layers of the first semiconductor material and the second semiconductor material, a first subset of the second epitaxial material stack being undoped, a second subset of the second epitaxial material stack being doped; patterning the first epitaxial material stack and the second epitaxial material stack to respectively form first nanowires and second nanowires; and forming a first gate structure around the first nanowires and a second gate structure around the second nanowires.

Embodiments herein describe techniques for a semiconductor device over a semiconductor substrate. A first bonding layer is above the semiconductor substrate. One or more nanowires are formed above the first bonding layer to be a channel layer. A gate electrode is around a nanowire, where the gate electrode is in contact with the first bonding layer and separated from the nanowire by a gate dielectric layer. A source electrode or a drain electrode is in contact with the nanowire, above a bonding area of a second bonding layer, and separated from the gate electrode by a spacer, where the second bonding layer is above and in direct contact with the first bonding layer.

A semiconductor structure includes the first semiconductor stack and the second semiconductor stack formed over the first region and the second region of a substrate, respectively. The first and second semiconductor stacks extend in the first direction and are spaced apart from each other in the second direction. Each of the first semiconductor stack and the second semiconductor stack includes channel layers and a gate structure. The channel layers are formed above the substrate and are spaced apart from each other in the third direction. The gate structure includes the gate dielectric layers formed around the respective channel layers, and the gate electrode layer formed on the gate dielectric layers to surround the channel layers. The number of channel layers in the first semiconductor stack is different from the number of channel layers in the second semiconductor stack.