InGaN offers a route to high efficiency overall water splitting under one-step photo-excitation. Further, the chemical stability of metal-nitrides supports their use as an alternative photocatalyst. However, the efficiency of overall water splitting using InGaN and other visible light responsive photocatalysts has remained extremely low despite prior art work addressing optical absorption through band gap engineering. Within this prior art the detrimental effects of unbalanced charge carrier extraction/collection on the efficiency of the four electron-hole water splitting reaction have remained largely unaddressed. To address this growth processes are presented that allow for controlled adjustment and establishment of the appropriate Fermi level and/or band bending in order to allow the photochemical water splitting to proceed at high rate and high efficiency. Beneficially, establishing such material surface charge properties also reduces photo-corrosion and instability under harsh photocatalysis conditions.

Provided herein are tapered nanowires that comprise germanium and gallium, as well as methods of forming the same. The described nanowires may also include one or more sections of a second semiconductor material. Methods of the disclosure may include vapor-liquid-solid epitaxy with a gallium catalyst. The described methods may also include depositing a gallium seed on a surface of a substrate by charging an area of the substrate using an electron beam, and directing a gallium ion beam across the surface of the substrate.

Self-aligned gate cutting techniques are disclosed herein that provide dielectric gate isolation fins for isolating gates of multigate devices from one another. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A dielectric gate isolation fin separates the first metal gate from the second metal gate. The dielectric gate isolation fin includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is greater than the first dielectric constant. The first metal gate and the second metal gate physically contact the first channel layer and the second channel layer, respectively, and the dielectric gate isolation fin.

A method includes providing a structure having a substrate and a stack of semiconductor layers over a surface of the substrate and spaced vertically one from another; forming an interfacial layer wrapping around each of the semiconductor layers; forming a high-k dielectric layer over the interfacial layer and wrapping around each of the semiconductor layers; and forming a capping layer over the high-k dielectric layer and wrapping around each of the semiconductor layers. With the capping layer wrapping around each of the semiconductor layers, the method further includes performing a thermal treatment to the structure, thereby increasing a thickness of the interfacial layer. After the performing of the thermal treatment, the method further includes removing the capping layer.

A method of manufacturing a device including micrometer- or nanometer-range wires including a III-V compound, including, for each wire, the forming of at least a portion of the wire by a step of metal-organic vapor epitaxy including the injection into a reactor of a first precursor gas of the group-V element, of a second precursor gas of the group-III element, and of a third precursor gas of an additional element, dopant of the III-V compound, of a gas capable of obtaining a dopant concentration greater than 5.10.sup.19 atoms/cm.sup.3, for example, greater than 1.10.sup.20 atoms/cm.sup.3, in the wire portion in the case where the portion has a homogeneous dopant concentration.

A composition of matter comprising: a plurality of group III-V nanowires or nanopyramids epitaxially grown on a polycrystalline or single-crystalline graphene layer, said graphene layer being directly supported on a crystalline substrate such as a group III-V semiconductor, sapphire, SiC or diamond substrate, wherein the epitaxy, crystal orientation and facet orientations of said nanowires or nanopyramids are directed by the crystalline substrate.

A method includes forming a first low-dimensional layer over an isolation layer, forming a first insulator over the first low-dimensional layer, forming a second low-dimensional layer over the first insulator, forming a second insulator over the second low-dimensional layer, and patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin. Remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator form a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively. A transistor is then formed based on the protruding fin.

The present disclosure relates to a nanowire structure, which includes a substrate with a substrate body and an ion implantation region, a patterned mask with an opening over the substrate, and a nanowire. Herein, the substrate body is formed of a conducting material, and the ion implantation region that extends from a top surface of the substrate body into the substrate body is electrically insulating. A surface portion of the substrate body is exposed through the opening of the patterned mask, while the ion implantation region is fully covered by the patterned mask. The nanowire is directly formed over the exposed surface portion of the substrate body and is not in contact with the ion implantation region. Furthermore, the nanowire is confined within the ion implantation region, such that the ion implantation region is configured to provide a conductivity barrier of the nanowire in the substrate.

Nanostructure field-effect transistors (NSFETs) including isolation layers formed between epitaxial source/drain regions and semiconductor substrates and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate; a gate stack over the semiconductor substrate, the gate stack including a gate electrode and a gate dielectric layer; a first epitaxial source/drain region adjacent the gate stack; and a high-k dielectric layer extending between the semiconductor substrate and the first epitaxial source/drain region, the high-k dielectric layer contacting the first epitaxial source/drain region, the gate dielectric layer and the high-k dielectric layer including the same material.

A wafer includes a substrate and at least one intermediate layer formed on a surface of the substrate. The at least one intermediate layer covers the surface of the substrate at least partially. An outer surface of the at least one intermediate layer is directed away from the surface of the substrate. The wafer further includes nanostructures grown on the outer surface of the at least one intermediate layer. The at least one intermediate layer is formed in such a way that positions of growth of the nanostructures are predetermined on the outer surface of the at least one intermediate layer. At least one nanostructure material of the nanostructures is assembled at the positions of growth of the nanostructures.