A method for manufacturing a semiconductor device includes forming a plurality of pillars on a substrate. Each pillar of the plurality of pillars includes a silicon germanium portion. In the method, a layer of germanium oxide is deposited on the plurality of pillars, and a thermal annealing process is performed to convert outer regions of the silicon germanium portions into a plurality of silicon nanotubes. Each silicon nanotube of the plurality of silicon nanotubes surrounds a silicon germanium core portion. The method also includes exposing top surfaces of each of the silicon germanium core portions, and selectively removing each of the silicon germanium core portions with respect to the plurality of silicon nanotubes to create a plurality of gaps.

Structures and methods that include selective electrostatic placement based on a dipole-to-dipole interaction of electron-rich carbon nanotubes onto an electron-deficient pre-patterned surface. The structure includes a substrate with a first surface having a first isoelectric point and at least one additional surface having a second isoelectric point. A self-assembled monolayer is selectively formed on the first surface and includes an electron deficient compound including a deprotonated pendant hydroxamic acid or a pendant phosphonic acid group or a pendant catechol group bound to the first surface. An organic solvent can be used to deposit the electron rich carbon nanotubes on the self-assembled monolayer.

A device includes a non-insulator structure, a first dielectric layer, and a first conductive feature. The first dielectric layer is over the non-insulator structure. The first conductive feature is in the first dielectric layer and includes carbon nano-tubes. The first catalyst layer is between the first conductive feature and the non-insulator structure. A top of the first catalyst layer is lower than a top of the first conductive feature.

Stacked SiGe nanotubes and techniques for the fabrication thereof are provided. In one aspect, a method of forming a SiGe nanotube stack includes: forming Si and SiGe layers on a wafer, one on top of another, in an alternating manner; patterning at least one fin in the Si and SiGe layers; depositing an oxide material onto the at least one fin; and annealing the at least one fin under conditions sufficient to diffuse Ge atoms from the SiGe layers along an interface between the oxide material and the Si and SiGe layers to form at least one vertical stack of SiGe nanotubes surrounding Si cores. A SiGe nanotube device and method for formation thereof are also provided.

A method of forming a semiconductor structure includes forming one or more fins disposed on a substrate, rounding surfaces of the one or more fins, forming faceted sidewalk from the rounded surfaces of the one or more fins, and forming a lateral semiconductor nanotube shell on the faceted sidewalk. The lateral semiconductor nanotube shell comprises a hexagonal shape.

A gas sensor includes a substrate, a thin film metallic glass, an ultrananocrystalline diamond layer and a sensor structure. The thin film metallic glass is formed on the substrate. The ultrananocrystalline diamond layer partially covers the thin film metallic glass. The sensor structure includes a seed layer formed on the ultrananocrystalline diamond layer and a plurality of nanostructures formed on the seed layer.

Disclosed herein is a semiconducting nanoparticle comprising a one-dimensional semiconducting nanoparticle having a first end and a second end; where the second end is opposed to the first end; and two first endcaps, one of which contacts the first end and the other of which contacts the second end respectively of the one-dimensional semiconducting nanoparticle; where the first endcap that contacts the first end comprises a first semiconductor and where the first endcap extends from the first end of the one-dimensional semiconducting nanoparticle to form a first nanocrystal heterojunction; where the first endcap that contacts the second end comprises a second semiconductor; where the first endcap extends from the second end of the one-dimensional semiconducting nanoparticle to form a second nanocrystal heterojunction; and where the first semiconductor and the second semiconductor are chemically different from each other.

A method includes forming a first low-dimensional layer over an isolation layer, forming a first insulator over the first low-dimensional layer, forming a second low-dimensional layer over the first insulator, forming a second insulator over the second low-dimensional layer, and patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin. Remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator form a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively. A transistor is then formed based on the protruding fin.

A method includes depositing a dielectric layer over a substrate, forming carbon nanotubes on the dielectric layer, forming a dummy gate stack on the carbon nanotubes, forming gate spacers on opposing sides of the dummy gate stack, and removing the dummy gate stack to form a trench between the gate spacers. The carbon nanotubes are exposed to the trench. The method further includes etching a portion of the dielectric layer underlying the carbon nanotubes, with the carbon nanotubes being suspended, forming a replacement gate dielectric surrounding the carbon nanotubes, and forming a gate electrode surrounding the replacement gate dielectric.

A semiconductor device includes a non-insulator structure, at least one carbon nano-tube (CNT), a dielectric layer, and a graphene-based conductive layer. The CNT is over the non-insulator structure. The dielectric layer surrounds the CNT. The graphene-based conductive layer is over the at least one CNT. The CNTs and the graphene-based conductive layer have low resistance.