Disclosed is a process for producing semiconductor nanowires having a diameter or thickness from 2 nm to 100 nm, the process comprising: (A) preparing a semiconductor material particulate having a size from 50 nm to 500 m, selected from Ga, In, Ge, Sn, Pb, P, As, Sb, Bi, Te, a combination thereof, a compound thereof, or a combination thereof with Si; (B) depositing a catalytic metal, in the form of nanoparticles having a size from 1 nm to 100 nm or a coating having a thickness from 1 nm to 100 nm, onto surfaces of the semiconductor material particulate to form a catalyst metal-coated semiconductor material; and (C) exposing the catalyst metal-coated semiconductor material to a high temperature environment, from 100 C. to 2,500 C., for a period of time sufficient to enable a catalytic metal-assisted growth of multiple semiconductor nanowires from the particulate.

A method of forming a semiconductor structure is provided. The method includes etching a trench in a template layer over a substrate, forming a seed structure over a bottom surface of the trench, forming a dielectric cap over the seed structure, and growing a single crystal semiconductor structure within the trench using a vapor liquid solid epitaxy growth process. The single crystal semiconductor structure is grown from a liquid-solid interface between the seed structure and the bottom surface of the trench.

Provided herein are tapered nanowires that comprise germanium and gallium, as well as methods of forming the same. The described nanowires may also include one or more sections of a second semiconductor material. Methods of the disclosure may include vapor-liquid-solid epitaxy with a gallium catalyst. The described methods may also include depositing a gallium seed on a surface of a substrate by charging an area of the substrate using an electron beam, and directing a gallium ion beam across the surface of the substrate.

The present application discloses a semiconductor device with nanowire plugs and a method for fabricating the semiconductor device. The semiconductor device includes a substrate having first regions and second regions; a plurality of capacitor contacts positioned over the second regions, at least one of the capacitor contacts having a neck portion and a head portion over the neck portion, wherein an upper width of the head portion is larger than an upper width of the neck portion; a plurality of bit line contacts positioned over the first regions and a plurality of bit lines positioned over the bit line contacts; a plurality of capacitor plugs disposed over the capacitor contacts, wherein at least one of the plurality of capacitor plugs includes a plurality of nanowires, a conductive liner disposed over the nanowires, and a conductor disposed over the conductive liner; and a plurality of capacitor structures disposed respectively over the capacitor plugs.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate having first regions and second regions; a plurality of bit line contacts and a plurality of capacitor contacts disposed over the plurality of first regions and second regions; a landing pad disposed over one of the plurality of capacitor contacts, the landing pad comprising a protruding portion of a capacitor plug and a first spacer disposed on a sidewall of the protruding portion; a conductive plug disposed over the landing pad; and a plurality of bit lines disposed over the plurality of bit line contacts; and a capacitor structure disposed over the conductive plug. The capacitor plug includes a plurality of nanowires, a conductive liner disposed over the plurality of nanowires, and a conductor disposed over the conductive liner.

According to one embodiment, a crystal growth method includes forming a first member at at least a part of a bottom portion of a hole in a structure body. The hole includes the bottom portion and a side portion. The first member includes a first element. The first element is not adhered to at least a part of the side portion in the forming the first member. The crystal growth method includes growing a crystal member inside the hole by supplying a source material to the hole after the forming the first member. The source material includes a second element. The crystal member includes the second element.

A composition of matter comprising at least one nanowire on a graphitic substrate, said at least one nanowire having been grown epitaxially on said substrate, wherein said nanowire comprises at least one group III-V compound or at least one group II-VI compound or comprises at least one non carbon group (IV) element.

The present invention provides a metal nitride platform for semiconductor devices, including, a pre-defined array of catalyst sites, disposed on a substrate. Metal nitride islands with lateral to vertical size ratios of at least greater than one (1) are disposed on the array of catalyst sites, where the surfaces of the metal nitride islands are with reduced dislocation densities and side walls with bending of dislocations. The platform of metal nitride islands is further used to build electrically and optically-active devices. The present invention also provides a process for the preparation of a metal nitride platform, selectively, on the array of catalyst sites, in the presence of a reactive gas and precursors and under preferred reaction conditions, to grow metal nitride islands with lateral to vertical size ratios of at least greater than one (1).

Provided herein are tapered nanowires that comprise germanium and gallium, as well as methods of forming the same. The described nanowires may also include one or more sections of a second semiconductor material. Methods of the disclosure may include vapor-liquid-solid epitaxy with a gallium catalyst. The described methods may also include depositing a gallium seed on a surface of a substrate by charging an area of the substrate using an electron beam, and directing a gallium ion beam across the surface of the substrate.

A semiconductor device includes: a semiconductor layer of a first conductivity type formed over a substrate; a plurality of semiconductor nanowires formed of a compound semiconductor of the first conductivity type extending above the semiconductor layer; and a gate electrode formed around the semiconductor nanowires in a connection portion between the semiconductor layer and the semiconductor nanowires.