A semiconductor device includes a semiconductor layer containing metal atoms, a charge storage layer provided on a surface of the semiconductor layer via a first insulating film, and an electrode layer provided on a surface of the charge storage layer via a second insulating film. The thickness of the first insulating film is 5 nm or more and 10 nm or less. The concentration of the metal atoms in the semiconductor layer is 5.0×10.sup.17 [EA/cm.sup.3] or higher and 1.3×10.sup.20 [EA/cm.sup.3] or lower.

In one embodiment, a semiconductor storage device includes a stacked body in which a plurality of conducting layers are stacked through a plurality of insulating layers in a first direction, a semiconductor layer penetrating the stacked body, extending in the first direction and including metal atoms, and a memory film including a first insulator, a charge storage layer and a second insulator that are provided between the stacked body and the semiconductor layer. The semiconductor layer surrounds a third insulator penetrating the stacked body and extending in the first direction, and at least one crystal grain in the semiconductor layer has a shape surrounding the third insulator.

A method of manufacturing a semiconductor nanowire semiconductor device is described. The method includes forming an amorphous channel material layer on a substrate, patterning the channel material layer to form semiconductor nanowires extending in a lateral direction on the substrate, and forming a cover layer covering an upper of the semiconductor nanowire. The cover layer and the nanowire are patterned to form a trench exposing a side section of an one end of the semiconductor nanowire and a catalyst material layer is formed in contact with a side surface of the semiconductor nanowire, and metal induced crystallization (MIC) by heat treatment is performed to crystallize the semiconductor nanowire in a length direction of the nanowire from the one end of the semiconductor nanowire in contact with the catalyst material.

A method of preparing crystalline graphene includes performing a first thermal treatment including supplying heat to an inorganic substrate in a reactor, introducing a vapor carbon supply source into the reactor during the first thermal treatment to form activated carbon, and binding of the activated carbon on the inorganic substrate to grow the crystalline graphene.

A vertical nanowire semiconductor device manufactured by a method of manufacturing a vertical nanowire semiconductor device is provided. The vertical nanowire semiconductor device includes a substrate, a first conductive layer in a source or drain area formed above the substrate, a semiconductor nanowire of a channel area vertically upright with respect to the substrate on the first conductive layer, wherein a crystal structure thereof is grown in <111> orientation, a second conductive layer of a drain or source area provided on the top of the semiconductor nanowire, a metal layer on the second conductive layer, a NiSi.sub.2 contact layer between the second conductive layer and the metal layer, a gate surrounding the channel area of the vertical nanowire, and a gate insulating layer located between the channel area and the gate.

A semiconductor device includes a semiconductor layer containing metal atoms, a charge storage layer provided on a surface of the semiconductor layer via a first insulating film, and an electrode layer provided on a surface of the charge storage layer via a second insulating film. The thickness of the first insulating film is 5 nm or more and 10 nm or less. The concentration of the metal atoms in the semiconductor layer is 5.0×10.sup.17 [EA/cm.sup.3] or higher and 1.3×10.sup.20 [EA/cm.sup.3] or lower.

A semiconductor device include a substrate, a buffer layer formed on the substrate, a channel layer formed by an intrinsic polycrystalline silicon layer on the buffer layer, polycrystalline source and drain by non-intrinsic silicon formed on both sides of the polycrystalline silicon layer, a source electrode and a drain electrode formed on the polycrystalline source and the drain, a gate electrode corresponding to the channel layer, and an NiSi.sub.2 contact layer located between the source and the source electrode and between the drain and the drain electrode.

The invention relates to a method for manufacturing a semiconductor component comprising a thin layer of crystalline silicon on a substrate, comprising the steps of: providing a silicon-rich aluminum substrate (S0), depositing a thin layer of amorphous silicon on the substrate (S1), and applying thermal annealing (S2) to the thin layer of amorphous silicon to obtain a thin layer of crystalline silicon on the substrate.

A method of manufacturing a semiconductor device includes steps of (i) forming a buffer layer of an insulating material on a substrate, (ii) forming a seed layer of catalyst material containing Ni on the buffer layer, (iii) forming, on the buffer layer, an amorphous intrinsic silicon layer for forming a channel, (iv) forming, on the amorphous intrinsic silicon layer, a non-intrinsic silicon layer for forming a source and/or drain, (v) forming a metal layer on the non-intrinsic silicon layer, and (vi) performing metal induced crystallization (MIC) process for crystallization of the amorphous intrinsic silicon layer and the amorphous non-intrinsic silicon layer, and activation of the amorphous non-intrinsic silicon layer to form a conductive area.

Provided is a method of manufacturing a semiconductor device, the method including: forming a buffer layer of an insulating layer on a substrate; a seed layer formation operation of forming, on the buffer layer, a seed layer of at least one selected from the group consisting of NiCxOy, NiNxOy, NiCxNyOz, NiCxOy:H, NiNxOy:H, NiCxNyOz:H, NixSiy, and NixGey; a silicon layer formation operation of forming an amorphous silicon layer on the seed layer; and a crystallization operation of crystallizing the amorphous silicon layer by a catalytic action of Ni by thermally treating the amorphous silicon layer.