Patent classifications
H01L21/02675
Laser irradiation apparatus, laser irradiation method, and method for manufacturing semiconductor device
A laser irradiation apparatus includes a laser generation device, a levitation unit to levitate an object to which the laser light is applied, and a conveyance unit to convey the levitated object. The conveyance unit includes a holding mechanism for holding the object by absorption, and a moving mechanism for moving the holding mechanism in a conveyance direction. The holding mechanism includes a base including a plurality of through holes, a plurality of pipes respectively connected to the through holes, a vacuum generation device configured to evacuate air from the pipes, and a plurality of absorption assistance valves each disposed in the middle of a respective one of the pipes, each of the plurality of absorption assistance valves being configured to be closed when a flow rate of a gas flowing into the pipe through the through hole becomes equal to or higher than a threshold.
Method for manufacturing semiconductor structure
Methods of manufacturing a semiconductor structure are provided. One of the methods includes the following operations. A substrate is received, and the substrate includes a first conductive region and a second conductive region. A first laser anneal is performed on the first conductive region to repair lattice damage. An amorphization is performed on the first conductive region and the second conductive region to enhance silicide formation to a desired phase transformation in the subsequent operations. A pre-silicide layer is formed on the substrate. A thermal anneal is performed to the substrate to form a silicide layer from the pre-silicide layer. A second laser anneal is performed on the first conductive region and the second conductive region.
Workpiece conveyance apparatus, semiconductor manufacturing apparatus, and workpiece conveyance method
A workpiece conveyance apparatus having: a conveyance path on which the workpiece moves; a gas flotation section that gas-floats the workpiece over the conveyance path; a movable holding section that holds the workpiece to move on the conveyance path along with the workpiece; and a treatment region conveyance path that is located on the conveyance path, and has a treatment region where predetermined treatment for the workpiece is performed, wherein the movable holding section has at least two or more holding sections along a movement direction of the conveyance path, each of the holding sections is capable of switching between release of holding and holding for the workpiece during movement of the workpiece, operation for releasing holding of the workpiece by the holding section on the treatment region conveyance path, and holding the workpiece on the conveyance path other than the treatment region conveyance path.
Low-Temperature Formation Of Thin-Film Structures
Methods for low-temperature formation of one or more thin-film semiconductor structures on a substrate that include the steps of, forming a (poly)silane layer over a substrate, transforming one or more parts of the (poly)silane layer in one or more thin-film solid-state semiconductor structures, by exposing the one or more parts with light from an
Source/drain structure
Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.
CRYSTALLINE TRANSITION METAL DICHALCOGENIDE FILMS AND METHODS OF MAKING SAME
Methods of making molybdenum sulfide (MoS.sub.2) on a stretchable substrate are disclosed. The method includes magnetron sputtering MoS.sub.2 onto a stretchable substrate, such as a stretchable polymeric material, at low temperatures to form a film precursor, and illumination annealing the film precursor to form high quality MoS.sub.2. The illumination source may be a laser or other source of radiation. Also, two-dimensional nanoelectronic devices made by the methods and/or from the high quality MoS.sub.2 are disclosed.
Method of fabricating array substrate, array substrate, and display apparatus
The present application provides an array substrate. The array substrate includes a base substrate; a light shielding layer on the base substrate; a metal oxide layer on a side of the light shielding layer distal to the base substrate; and an active layer on a side of the metal oxide layer distal to the base substrate. The metal oxide layer includes a metal oxide material. The light shielding layer includes amorphous silicon. An orthographic projection of the light shielding layer on the base substrate substantially overlaps with an orthographic projection of the active layer on the base substrate, and substantially overlaps with an orthographic projection of the metal oxide layer on the base substrate.
Thin film transistor and manufacturing method thereof, display device
A thin film transistor, its manufacturing method, and a display device are provided. The method comprises: forming a gate metal layer (35), forming a step-like gate structure (352) by one patterning process; performing a first ion implantation procedure to forming a first heavily doped area (39a) and a second heavily doped area (39b), the first heavily doped area (39a) being separated apart from the second heavily doped area (39b) by a first length; forming a gate electrode (353) from the step-like gate structure (352); performing a second ion implantation procedure to form a first lightly doped area (38a) and a second lightly doped area (38b), the first lightly doped area (38a) being separated apart from the second lightly doped area (38b) by a second length less than the first length. By the above method, the process for manufacturing the LTPS TFT having the lightly doped source/drain structure can be simplified.
Thin film transistor, method for fabricating the same, and array substrate
Embodiments of the present invention provide a thin film transistor, a method for fabricating the same and an array substrate. The thin film transistor comprises a base substrate and an active region and a plurality of reflective plates formed on the base substrate, wherein the plurality of reflective plates are spaced apart from each other and provided at least at positions corresponding to the active region, the active region comprises polysilicon, and the polysilicon in the active region is formed by irradiating an amorphous silicon layer with laser emitted from a side of the amorphous silicon layer away from the reflective plates.
THIN FILM TRANSISTOR, MANUFACTURING PROCESS FOR THIN FILM TRANSISTOR, AND LASER ANNEALING APPARATUS
The present invention provides a thin film transistor including a gate electrode, a source electrode, a drain electrode, and a semiconductor layer, which are laminated on a substrate. The semiconductor layer is a polysilicon thin film. The polysilicon thin film in regions corresponding to the source electrode and the drain electrode has a smaller crystal grain size than that of the polysilicon thin film in a channel region between the source electrode and the drain electrode.