The present disclosure is directed to a methodology for embedding a deterministic number of dopant atoms in a surface portion of a group IV semiconductor lattice. The methodology comprises the steps of: forming one or more lithographic sites on the surface portion; dosing, at a temperature below 100 K, the surface portion using a gas with molecules comprising the dopant atom and hydrogen atoms in a manner such that, a portion of the molecules bonds to the surface portion; and incorporating one or more dopant atoms in a respective lithographic site by transferring an amount of energy to the dopant atoms. The number of dopant atoms incorporated in a lithographic site is deterministic and related to the size of the lithographic site.

A TVS device and a manufacturing method therefor. The TVS device comprises: a first doping type semiconductor substrate (100); a second doping type deep well I (101), a second doping type deep well II (102), and a first doping type deep well (103) provided on the semiconductor substrate; a second doping type heavily doped region I (104) provided in the second doping type deep well I (101); a first doping type well region (105) and a first doping type heavily doped region I (106) provided in the second doping type deep well II (102); a first doping type heavily doped region II (107) and a second doping type heavily doped region II (108) provided in the first doping type deep well (105); a second doping type heavily doped region III (109) located in the first doping type well region (105) and the second doping type deep well II (102); and a first doping type doped region (110) provided in the first doping type well region (105).

An apparatus is provided which comprises: a fin; a layer formed on the fin, the layer dividing the fin in a first section and a second section; a first device formed on the first section of the fin; and a second device formed on the second section of the fin.

Techniques for forming VFET bottom source and drain epitaxy with anchors are provided. In one aspect, a method of forming a VFET device includes: patterning at least one fin in a substrate; forming anchors on opposite ends of the at least one fin; laterally etching a base of the at least one fin, wherein the anchors prevent the lateral etching from being performed on the ends of the at least one fin; forming bottom source and drains at the base of the at least one fin between the anchors; removing the anchors; forming bottom spacers on the bottom source and drains; forming gates above the bottom spacers alongside the at least one fin; forming top spacers above the gates; and forming top source and drains above the top spacers at a top of the at least one fin. VFET devices are also provided.

A method of producing a bifacial photovoltaic cell is disclosed herein, the method comprising: forming a boron-containing layer on a second surface of a semiconductor substrate; forming a cap layer above the boron-containing layer; effecting simultaneously: i) deposition on the first surface and ii) diffusion into it of the phosphorous using POCl.sub.3 gas phase process and iii) diffusion of the boron into the second surface of the substrate, to thereby dope the first surface with n-dopant and the second surface with boron.

There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate; a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, wherein the second source/drain layer comprises a first semiconductor material which is stressed; and a gate stack surrounding a periphery of the channel layer.

There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate, and a first device and a second device formed on the substrate. Each of the first device and the second device includes a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and also a gate stack surrounding a periphery of the channel layer. The channel layer of the first device and the channel layer of the second device are substantially co-planar.

A method for manufacturing and a Super Junction MOSFET are disclosed. The Super Junction MOSFET comprises a lightly doped epitaxial layer of a first conductivity type on a heavily doped substrate of the first conductivity type. A deep trench is formed in the epitaxial layer. The deep trench having an insulating layer with a thickness gradient formed on surfaces of the deep trench. One or more regions of the epitaxial layer proximate to sidewalls of the deep trench is doped of a second conductivity type, wherein the second conductivity type is opposite the first conductivity type. Finally, MOSFET device structures are formed in the epitaxial layer.

A vertical storage device, a method of manufacturing the same, and an electronic apparatus including the storage device are provided. The storage device includes: a first source/drain layer located at a first height with respect to a substrate and a second source/drain layer located at a second height different from the first height; a channel layer connecting the first source/drain layer and the second source/drain layer; and a gate stack including a storage function layer, the storage function layer extending on a sidewall of the channel layer and extending in-plane from the sidewall of the channel layer onto a sidewall of the first source/drain layer and a sidewall of the second source/drain layer.

A SiO.sub.2 layer 5 is formed in the bottom portion of a Si pillar 3 and on an i-layer substrate 2. Subsequently, a gate HfO.sub.2 layer 11b is formed so as to surround the side surface of the Si pillar 3, and a gate TiN layer 12b is formed so as to surround the HfO.sub.2 layer 11b. Subsequently, P.sup.+ layers 18 and 32 containing an acceptor impurity at a high concentration and serving as a source and a drain are simultaneously or separately formed by a selective epitaxial crystal growth method on the exposed side surface of the bottom portion of and on the top portion of the Si pillar 3. Thus, an SGT is formed on the i-layer substrate 2.