Epitaxy troughs are formed in a semiconductor substrate, wherein a matrix section of the semiconductor substrate laterally separates the epitaxy troughs and comprises a first semiconductor material. Crystalline epitaxy regions of a second semiconductor material are formed in the epitaxy troughs, wherein the second semiconductor material differs from the first semiconductor material in at least one of porosity, impurity content or defect density. From the epitaxy regions at least main body portions of semiconductor bodies of the semiconductor devices are formed.

A method of processing a semiconductor device, comprising: providing a semiconductor body having dopants of a first conductivity type; forming at least one trench that extends into the semiconductor body along a vertical direction, the trench being laterally confined by two trench sidewalls and vertically confined by a trench bottom; applying a substance onto at least a section of a trench surface formed by one of the trench sidewalls and/or the trench bottom of the at least one trench, such that applying the substance includes preventing that the substance is applied to the other of the trench sidewalls; and diffusing of the applied substance from the section into the semiconductor body, thereby creating, in the semiconductor body, a semiconductor region having dopants of a second conductivity type and being arranged adjacent to the section.

A semiconductor device including a gate structure on a channel region portion of a fin structure, and at least one of an epitaxial source region and an epitaxial drain region on a source region portion and a drain region portion of the fin structure. At least one of the epitaxial source region portion and the epitaxial drain region portion include a first concentration doped portion adjacent to the fin structure, and a second concentration doped portion on the first concentration doped portion. The second concentration portion has a greater dopant concentration than the first concentration doped portion. An extension dopant region extending into the channel portion of the fin structure having an abrupt dopant concentration gradient of n-type or p-type dopants of 7 nm per decade or greater.

A device including a vertical fin bipolar junction transistor (BJT) with graded doping SiGe base with molecular layer doping (MLD), where a lower doped base is grown and a top emitter is formed and then additional late doping is provided on an Si layer on a side of the emitter and a method of manufacture thereof.

A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 510.sup.21 to about 510.sup.22 atoms/cm.sup.2.

A surface region of a semiconductor material on a surface of a semiconductor device is doped during its manufacture, by coating the surface region of the semiconductor material with a dielectric material surface layer and locally heating the surface of the semiconductor material in an area to be doped to locally melt the semiconductor material with the melting being performed in the presence of a dopant source. The heating is performed in a controlled manner such that a region of the surface of the semiconductor material in the area to be doped is maintained in a molten state without refreezing for a period of time greater than one microsecond and the dopant from the dopant source is absorbed into the molten semiconductor. The semiconductor device includes a semiconductor material structure in which a junction is formed and may incorporate a multi-layer anti-reflection coating. The anti-reflection coating is located on a light receiving surface of the semiconductor material structure and comprises a thin layer of thermal expansion mismatch correction material having a thermal expansion coefficient less than or equal to that of the semiconductor material, to provide thermal expansion coefficient mismatch correction. An anti-reflection layer is provided having a refractive index and thickness selected to match the semiconductor material structure so as to give good overall antireflection properties to the solar cell.

A double diffusion break (DDB) gate structure is provided by removing the vestigial antenna to provide a space and the space is filled, at least in part, with an interlevel dielectric (ILD) material. Removal of the vestigial antenna from the DDB gate structure will reduce the device capacitance and improve device performance, while enabling DDB in tight integration schemes.

The present application provides a detection method of metal impurity in wafer. The method comprises conducting a medium temperature thermal treatment for a first predicted time period to the wafer, cooling the wafer and conducting a low temperature thermal treatment for a second predicted time period, cooling the wafer to ambient temperature; providing a liquid of vapor phase decomposition on the wafer to collect metal impurities; atomizing the liquid containing the collected metal impurities, conducting an inductively coupled plasma mass spectrometry analysis and obtaining concentrations of the metal impurities. The present application applies the combination of various thermal treatment without an interrupt of cooling to ambient temperature to contemplate diffusions of various metal impurities to the wafer surface. Accordingly, the detection of metal impurities can be conducted with reduced time cost and enhanced efficiency.

A double diffusion break (DDB) gate structure is provided by removing the vestigial antenna to provide a space and the space is filled, at least in part, with an interlevel dielectric (ILD) material. Removal of the vestigial antenna from the DDB gate structure will reduce the device capacitance and improve device performance, while enabling DDB in tight integration schemes.

Disclosed herein are methods of doping a fin-shaped channel region of a partially fabricated 3-D transistor on a semiconductor substrate. The methods may include forming a multi-layer dopant-containing film on the substrate, forming a capping film comprising a silicon carbide material, a silicon nitride material, a silicon carbonitride material, or a combination thereof, the capping film located such that the multi-layer dopant-containing film is located in between the substrate and the capping film, and driving dopant from the dopant-containing film into the fin-shaped channel region. Multiple dopant-containing layers of the film may be formed by an atomic layer deposition process which includes adsorbing a dopant-containing film precursor such that it forms an adsorption-limited layer on the substrate and reacting adsorbed dopant-containing film precursor. Also disclosed herein are multi-station substrate processing apparatuses for doping the fin-shaped channel regions of partially fabricated 3-D transistors.