H01L21/28506

Deposition mask group, manufacturing method of electronic device, and electronic device

A deposition mask group includes a first deposition mask having two or more first through holes arranged along two different directions, a second deposition mask having two or more second through holes arranged along two different directions and a third deposition mask having two or more third through holes. The first through hole and the second through hole or the third through hole partly overlap when the first deposition mask, the second deposition mask and the third deposition mask are overlapped.

ATOMIC LAYER DEPOSITION METHOD FOR METAL THIN FILMS

Provided is a method for depositing a metal thin film by atomic layer deposition (ALD) using an organometallic complex as a source material and without using radical species such as plasma and ozone, which have a possibility of deactivation. The method is an atomic layer deposition (ALD) method for metal thin films which includes: a process of supplying an organometallic complex having an aromatic anionic ligand and/or an alkyl ligand into a reaction chamber in which a substrate is installed; and a process of supplying a mixture gas containing a nucleophilic gas and an electrophilic gas into the reaction chamber, the ALD method substantially not using either one of a gas in a plasma or radical state and a gas containing oxygen atoms.

SEMICONDUCTOR STRUCTURE WITH AIR GAP IN PATTERN-DENSE REGION AND METHOD OF MANUFACTURING THE SAME
20240055261 · 2024-02-15 ·

The present disclosure provides a semiconductor structure, which includes: a first conductive layer arranged over a substrate; a dielectric layer arranged over the first conductive layer; a plurality of first conductive plugs penetrating through the dielectric layer; a plurality of spacers surrounding the respective first conductive plugs; a lining layer covering the dielectric layer, the spacer and the first conductive plugs, wherein the lining layer and the first conductive plugs include manganese (Mn); a second conductive plug penetrating through the lining layer; and a second conductive layer over the lining layer and the second conductive plug.

METAL INSULATOR METAL CAPACITOR WITH EXTENDED CAPACITOR PLATES
20190341307 · 2019-11-07 ·

A capacitor structure is described. A metal insulator metal capacitor in an integrated circuit device includes a first dielectric layer on a substrate. The first dielectric layer has a linear trench feature in which the capacitor is disposed. A bottom capacitor plate is in a lower portion of the trench. The bottom capacitor plate has an extended top face so that the extended top face extends upwards in a central region of the bottom capacitor plate metal relative to side regions. A high-k dielectric layer is disposed over the extended top face of the bottom capacitor plate. A top capacitor plate is disposed in a top, remainder portion of the trench on top of the high-k dielectric layer.

SELECTIVE DEPOSITION OF HARDMASK

One or more embodiments described herein generally relate to selective deposition of substrates in semiconductor processes. In these embodiments, a precursor is delivered to a process region of a process chamber. A plasma is generated by delivering RF power to an electrode within a substrate support surface of a substrate support disposed in the process region of the process chamber. In embodiments described herein, delivering the RF power at a high power range, such as greater than 4.5 kW, advantageously leads to greater plasma coupling to the electrode, resulting in selective deposition to the substrate, eliminating deposition on other process chamber areas such as the process chamber side walls. As such, less process chamber cleans are necessary, leading to less time between depositions, increasing throughput and making the process more cost-effective.

RF GROUNDING CONFIGURATION FOR PEDESTALS

Embodiments of the present disclosure generally relate to substrate supports for process chambers and RF grounding configurations for use therewith. Methods of grounding RF current are also described. A chamber body at least partially defines a process volume therein. A first electrode is disposed in the process volume. A pedestal is disposed opposite the first electrode. A second electrode is disposed in the pedestal. An RF filter is coupled to the second electrode through a conductive rod. The RF filter includes a first capacitor coupled to the conductive rod and to ground. The RF filter also includes a first inductor coupled to a feedthrough box. The feedthrough box includes a second capacitor and a second inductor coupled in series. A direct current (DC) power supply for the second electrode is coupled between the second capacitor and the second inductor.

Method and apparatus for chemical vapour deposition
11970765 · 2024-04-30 · ·

The present disclosure relates to a method for chemical vapour deposition on a substrate, the method comprising a precursor step and a reactant step, wherein the precursor step comprises chemisorbing a layer of precursor molecules on the substrate (170), and wherein the reactant step comprises adding to at least part of the substrate (170) surface species able to reduce the precursor molecule, whereby at least a part of the reduced precursor molecule is deposited on the substrate (170) surface, characterized by applying by means of a voltage source (130) a positive bias to at least part of the substrate (170) surface during at least part of the reactant step, wherein the step of adding the reducing species comprises providing by means of an electron source (150) electrons as free particles, whereby during the reactant step a closed electrical circuit is formed as the free electrons are transmitted to the substrate (170) surface.

SEMICONDUCTOR PACKAGING METHOD
20240136190 · 2024-04-25 ·

Provided is a method for packing a semiconductor, and more particularly, to a method for packaging a semiconductor, which packages the semiconductor device in a wafer level packaging manner. The method for packaging the semiconductor includes: preparing a wafer including a plurality of semiconductor devices; and forming a conductive pattern layer electrically connected to the plurality of semiconductor devices by using a mask member that is provided separately from the wafer.

TUNING WORK FUNCTION OF P-METAL WORK FUNCTION FILMS THROUGH VAPOR DEPOSITION

The present disclosure relates to a method for forming a p-metal work function nitride film having a desired p-work function on a substrate, including: adjusting one or more of a temperature of a substrate, a duration of one or more temporally separated vapor phase pulses, a ratio of a tungsten precursor to a titanium precursor, or a pressure of a reaction to tune a work function of a p-metal work function nitride film to a desired p-work function, and contacting the substrate with temporally separated vapor phase pulses of the tungsten precursor, the titanium precursor, and a reactive gas to form a p-metal work function nitride film thereon having the desired p-work function.

Method of Manufacturing Semiconductor Device and Non-Transitory Computer-Readable Recording Medium

Described herein is a technique capable of improving a quality of a substrate processing. According to one aspect of the technique described herein, there is provided a method of manufacturing a semiconductor device including: (a) receiving substrate data including at least one of a stacked number of layers of a device formed on a substrate and a structure of the device; (b) setting an apparatus parameter corresponding to the substrate data; (c) supporting the substrate corresponding to the substrate data above a substrate support; (d) elevating a temperature of the substrate based on the apparatus parameter while the substrate is separated from a surface of the substrate support; (e) placing the substrate on the substrate support after (d); and (f) processing the substrate in a process chamber.