Sequential electrodeposition of metals into through-mask features on a semiconductor substrate is conducted such as to reduce the deleterious consequences of lipseal's pressure onto the mask material. In a first electroplating step, a first metal (e.g., nickel) is electrodeposited using a lipseal that has an innermost point of contact with the semiconductor substrate at a first distance from the edge of the substrate. In a second electroplating step, a second metal (e.g., tin) is electrodeposited using a lipseal that has an innermost point of contact with the semiconductor substrate at a greater distance from the edge of the substrate than the first distance. This allows to at least partially shift the lipseal pressure from a point that could have been damaged during the first electrodeposition step and to shield from electrolyte any cracks that might have formed in the mask material during the first electroplating step.

A plating apparatus for electroplating a wafer includes a housing defining a plating chamber for housing a plating solution. A voltage source of the apparatus has a first terminal having a first polarity and a second terminal having a second polarity different than the first polarity. The first terminal is electrically coupled to the wafer. An anode is within the plating chamber, and the second terminal is electrically coupled to the anode. A membrane support is within the plating chamber and over the anode. The membrane support defines apertures, wherein in a first zone of the membrane support a first aperture-area to surface-area ratio is a first ratio, and in a second zone of the membrane support a second aperture-area to surface-area ratio is a second ratio, different than the first ratio.

A plating apparatus and an operation method thereof are provided. The plating apparatus includes: a tank body including at least one side wall, the at least one side wall being provided with an opening extending from the inside to the outside of the tank body, and the tank body being configured to accommodate a plating solution; and a fixing device configured to fix the substrate at the opening of the side wall. The operation method of the plating apparatus includes: placing the substrate on an outer side of the side wall and at the position of the opening, and operating the fixing device to fix the substrate; and performing plating treatment on the substrate.

Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.

A method of fabricating a semiconductor device is disclosed. The method includes forming a dielectric layer over a substrate. The substrate has an edge region and a center region. The method also includes forming a dielectric ring in the edge region, forming a metal layer over the center region of the substrate and over the dielectric ring in the edge region of the substrate and polishing the metal layer in the center region and the edge region to expose the dielectric ring in the edge region of the substrate.

A method for fabricating high-resolution features in a deep recess includes etching a cavity in a substrate, fabricating at least one focusing pattern on a bottom of the cavity, wherein fabricating the focusing pattern comprises coating a first photoresist on the bottom of the cavity, patterning the first photoresist to define a focusing etch area using contact lithography, and etching the focusing etch area, coating a second photoresist on the bottom of the cavity, using the focusing pattern to focus a high resolution lithography tool at the bottom of the cavity to pattern the second photoresist to define a microfabrication feature area; and forming a microfabrication feature in the microfabrication feature area.

Provided are a Cu column, a Cu core column, a solder joint, and a through-silicon via, which have the low Vickers hardness and the small arithmetic mean roughness. For the Cu column 1 according to the present invention, its purity is equal to or higher than 99.9% and equal to or lower than 99.995%, its arithmetic mean roughness is equal to or less than 0.3 μm, and its Vickers hardness is equal to or higher than 20 HV and equal to or less than 60 HV. Since the Cu column 1 is not melted at a melting temperature in the soldering and a definite stand-off height (a space between the substrates) can be maintained, it is preferably applied to the three dimensional mounting or the pitch narrowing mounting.

Methods of metalizing vias within a substrate are disclosed. In one embodiment, a method of metalizing vias includes disposing a substrate onto a growth substrate. The substrate includes a first surface, a second surface, and at least one via. The first surface or the second surface of the substrate directly contacts a surface of the growth substrate, and the surface of the growth substrate is electrically conductive. The method further includes applying an electrolyte to the substrate such that the electrolyte is disposed within the at least one via. The electrolyte includes metal ions of a metal to be deposited within the at least one via. The method also includes positioning an electrode within the electrolyte, and applying a current and/or a voltage between the electrode and the substrate, thereby reducing the metal ions into the metal on the surface of the growth substrate within the at least one via.

A substrate processing apparatus includes a holding device that includes a conductive member and holds a substrate, a conduction path structure that includes a conductive material and positioned such that the conduction path structure is in contact with the holding device, a supply device that supplies a processing liquid to the substrate held by the holding device, and a grounding structure including a variable resistance device that changes a resistance such that the grounding structure has a first end portion connected the conduction path structure and a second end portion connected to a ground potential.

Provided is a semiconductor device, including: a front-back conduction-type semiconductor element; a front-side electrode formed on the front-back conduction-type semiconductor element; an electroless nickel-containing plating layer formed on the front-side electrode; and an electroless gold plating layer formed on the electroless nickel-containing plating layer, wherein the semiconductor device has a low-nickel concentration layer on a side of the electroless nickel-containing plating layer in contact with the electroless gold plating layer, and wherein the low-nickel concentration layer has a thickness smaller than that of the electroless gold plating layer.