Various embodiments herein relate to methods and apparatus for electroplating cobalt on a substrate. In many cases, the cobalt is electroplated into recessed features. The recessed features may include a seed layer such as a cobalt seed layer. Electroplating may occur through a bottom-up mechanism. The bottom-up mechanism may be achieved by using particular additives (e.g., accelerator and suppressor), which may be present in the electrolyte at particular concentrations. Further, leveler, wetting agent, and/or brightening agents may be used to promote high quality plating results. In various embodiments, the substrate is pre-treated to remove oxide (and in some cases carbon impurities) from the seed layer before electroplating takes place. Further, the electrolyte may have a particular conductivity to promote uniform plating results across the face of the substrate.

A nano-twinned copper layer is disclosed, wherein over 50% of a volume of the nano-twinned copper layer comprises a plurality of columnar crystal grains, the plurality of columnar crystal grains connect to each other, at least 70% of the plurality of columnar crystal grains are formed by a plurality of nano-twins stacking in an orientation of a crystal axis, and an angle included between two adjacent columnar crystal grains is greater 20° and less than or equal to 60°. In addition, a method for manufacturing the nano-twinned copper layer and a substrate comprising the same are also disclosed.

A method for producing a plated formed product includes: a step (1) of forming on a substrate of the substrate having a metal film a resin film of a photosensitive resin composition containing a sulfur-containing compound having at least one selected from a mercapto group, a sulfide bond, and a polysulfide bond; a step (2) of exposing the resin film; a step (3) of developing the exposed resin film to form a resist pattern film; a step (4) of performing plasma treatment of a substrate having the resist pattern film on the metal film with oxygen-containing gas; and a step (5) of performing, after the plasma treatment, plating treatment with the resist pattern film as a mold.

The method comprises providing a plurality of electronic devices, embedding the electronic devices in an encapsulation layer, forming vias into the encapsulation layer, the vias extending from a main face of the encapsulation layer to the electronic devices, and depositing a metallic layer onto the encapsulation layer including the vias by galvanic plating, the method further comprising providing a current distribution layer for effecting a distributed growth of the metallic material during the galvanic plating.

Disclosed herein is an interconnect structure, including: a dielectric material layer having a cavity having a height, width and length within a dielectric material layer wherein the width is less than or equal to about 100 nanometers and the height to width ratio is less than or equal to about 2.5; a diffusion barrier liner layer disposed in the cavity on the dielectric material; an optional crystallization seed layer disposed on the diffusion barrier liner layer; and a conductive material disposed on the crystallization seed layer when present and filling the opening. When the crystallization seed layer is not present the conductive material is disposed on the diffusion barrier liner.

Exemplary methods of producing a semiconductor substrate may include plating a metal within a plurality of vias on the semiconductor substrate. A target average fill thickness of the metal within the plurality of vias may be between about a thickness equal to an average via radius of the plurality of vias and a thickness twice the average via radius of the plurality of vias. At least one via of the plurality of vias may be filled to a height below the target average fill thickness of the metal. The methods may include heating the metal to cause reflow of the metal within each via of the plurality of vias. The reflow may adjust the metal within the at least one via to increase in height towards the target average fill thickness.

Disclosed are pre-wetting apparatus designs and methods. These apparatus designs and methods are used to pre-wet a wafer prior to plating a metal on the surface of the wafer. Disclosed compositions of the pre-wetting fluid prevent corrosion of a seed layer on the wafer and also improve the filling rates of features on the wafer.

A contact ring for an electroprocessor has redundant contact fingers, i.e., more contact fingers than needed for contacting a very narrow edge exclusion zone on a substrate such as a semiconductor wafer. The contact fingers have slightly different lengths so that they extend to different radial positions. By providing redundant contact fingers, and by slightly varying the lengths of the contact fingers, a sufficient number of contact fingers make contact with the electrically conductive surface in the edge exclusion zone to provide good electroplating results.

Nanocomposite magnetic materials, methods of manufacturing nanocomposite magnetic materials, and magnetic devices and systems using these nanocomposite magnetic materials are described. A nanocomposite magnetic material can be formed using an electro-infiltration process where nanomaterials (synthesized with tailored size, shape, magnetic properties, and surface chemistries) are infiltrated by electroplated magnetic metals after consolidating the nanomaterials into porous microstructures on planar substrates. The nanomaterials may be considered the inclusion phase, and the magnetic metals may be considered the matrix phase of the multi-phase nanocomposite.

A method of manufacturing a semiconductor device includes providing a first semiconductor chip comprising a first metallic structure, a first surface and a second surface opposite to the first surface; providing a second semiconductor chip comprising a second metallic structure; bonding the first semiconductor chip with the second semiconductor chip on the second surface; forming a first recessed portion including a first sidewall and a first bottom surface coplanar with a top surface of the first metallic structure; forming a second recessed portion including a second sidewall and a second bottom surface coplanar with a top surface of the second metallic structure; forming a dielectric layer over the first sidewall and the second sidewall; and forming a conductive material over the dielectric layer, the top surface of the first metallic structure and the top surface of the second metallic structure.