In an embodiment, a method includes: receiving, within a processing chamber, a wafer with a photoresist mask above a metal layer, wherein the processing chamber is connected to a gas source; applying an etchant configured to etch the metal layer in accordance with the photoresist mask within the processing chamber; and applying gas from the gas source to perform plasma ashing in the processing chamber.

Techniques herein include methods for coating a single layer actuator film or multi-layer actuator film on the backside of a wafer. The actuator film includes one or more chemical actuators. Chemical actuators are various molecules, crystals, chemical compounds and other chemical compositions that are capable of imposing directional stress in response to application of an external stimulus on the chemical actuator. The external stimulus can include a particular wavelength of light or polarization of light, or heat (or directed infrared radiation) or load, which can include load-responsive actuation or pressure-responsive actuation.

Systems and methods for shaping a film. The method of shaping a film may comprise dispensing a polymerizable fluid as a plurality of droplets onto a substrate. The method of shaping a film may further comprise bringing an initial superstrate contact region of a superstrate into contact with an initial subset of droplets of the plurality of droplets. The initial subset of droplets may merge and form an initial fluid film over the initial substrate contact region. The method of shaping a film may further comprise prior to the superstrate coming into contact with the remaining plurality of droplets on the substrate, polymerizing a region of the initial fluid film on the initial substrate contact region.

A semiconductor wafer dicing process is disclosed for dicing a wafer into individual dies. Scribe lines are formed within a polymer coating to expose regions of wafer to form a pre-processed product. The pre-processed product within the chamber is plasma etched to remove the exposed regions of the wafer to separate the individual dies and form a processed product. A frame cover is then removed and the processed product, wafer frame and adhesive tape are exposed to an oxygen plasma within the chamber to partially remove an outermost region of the polymer coating, which is most heavily contaminated with fluorine, to leave a residual polymer coating on the individual dies and form a post-processed product. The residual polymer coating on the individual dies of the post-processed product is then removed.

Disclosed is a packaging method for circuit units, wherein the circuit units comprise a silicon layer substrate and a silicon dioxide layer overlaid on the silicon layer substrate. The packaging method for a circuit unit comprises: attaching a plurality of circuit units to a circuit baseplate in a spaced and inverted mode, wherein the silicon dioxide layer is attached to the circuit baseplate, and the silicon layer substrate faces away from the circuit baseplate; forming an insulator between the circuit units; removing the silicon layer substrate to expose the silicon dioxide layer; and forming an electromagnetic shielding layer on the silicon dioxide layer and the insulator.

A self-assembled nanostructure comprises first domains and second domains. The first domains comprise a first block of a block copolymer material and an activatable catalyst. The second domains comprise a second block and substantially without the activatable catalyst. The activatable catalyst is capable of generating catalyst upon application of activation energy, and the generated catalyst is capable of reacting with a metal oxide precursor to provide a metal oxide. A semiconductor structure comprises such self-assembled nanostructure on a substrate.

An end of polishing of a wafer is determined for each of wafers at a high accuracy. A wafer processing method includes: a first process of acquiring an initial state of a processing target surface of a wafer; a second process of forming a coating film on the wafer after the first process; a third process of polishing the processing target surface of the wafer by a polishing member based on initial polishing conditions in a state where the polishing member is in contact with the processing target surface of the wafer; a fourth process of acquiring a processed state of the processing target surface of the wafer after the third process; and a fifth process of determining an end of polishing, an insufficiency in polishing, or an excess in polishing based on the initial state and the processed state.

A pattern formation method includes forming an organic film on a substrate, processing the organic film to form an organic film pattern, exposing the organic film pattern to an organic gas, and exposing the organic film pattern to a metal-containing gas, and after (i) exposing the organic film pattern to the organic gas and (ii) exposing the organic film pattern to the metal-containing gas, treating the organic film pattern with an oxidizing agent.

A method of planarizing a substrate comprises dispensing formable material onto a substrate, contacting a superstrate held by a superstrate chuck with the formable material on the substrate, thereby forming a multilayer structure including the superstrate, a film of the formable material, and the substrate, releasing the multilayer structure from the superstrate chuck, providing a space between the superstrate chuck and the multilayer structure after the releasing, positioning a light source into the provided space between the superstrate chuck and the multilayer structure, and curing the film of the multilayer structure by exposing the film to light emitted from the light source.

Some embodiments include a semiconductor construction which has one or more openings extending into a substrate. The openings are at least partially filled with dielectric material comprising silicon, oxygen and carbon. The carbon is present to a concentration within a range of from about 3 atomic percent to about 20 atomic percent. Some embodiments include a method of providing dielectric fill across a semiconductor construction having an opening extending therein. The semiconductor construction has an upper surface proximate the opening. The method includes forming photopatternable dielectric material within the opening and across the upper surface, and exposing the photopatternable dielectric material to patterned actinic radiation. Subsequently, the photopatternable dielectric material is developed to pattern the photopatternable dielectric material into a first dielectric structure which at least partially fills the opening, and to remove the photopatternable dielectric material from over the upper surface.