Described is a process to clean up junction interfaces for fabricating semiconductor devices involving forming low-resistance electrical connections between vertically separated regions. An etch can be performed to remove silicon oxide on silicon surface at the bottom of a recessed feature. Described are methods and apparatus for etching up the bottom oxide of a hole or trench while minimizing the effects to the underlying epitaxial layer and to the dielectric layers on the field and the corners of metal gate structures. The method for etching features involves a reaction chamber equipped with a combination of capacitively coupled plasma and inductive coupled plasma. CH.sub.xF.sub.y gases and plasma are used to form protection layer, which enables the selectively etching of bottom silicon dioxide by NH.sub.3—NF.sub.3 plasma. Ideally, silicon oxide on EPI is removed to ensure low-resistance electric contact while the epitaxial layer and field/corner dielectric layers are—etched only minimally or not at all.

A method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.

Semiconductor devices and methods which utilize a treatment process of a bottom anti-reflective layer are provided. The treatment process may be a physical treatment process in which material is added in order to fill holes and pores within the material of the bottom anti-reflective layer or else the treatment process may be a chemical treatment process in which a chemical reaction is used to form a protective layer. By treating the bottom anti-reflective layer the diffusion of subsequently applied chemicals is reduced or eliminated, thereby helping to prevent defects that arise from such diffusion.

A substrate is provided with a patterned layer, such as, a photo resist layer which may exhibit line roughness. The patterned layer may be an EUV photo resist layer utilized in a self-aligned multi-patterning process. A tone inversion process having a tone inversion layer is utilized along with a surface treatment of a sidewall of the tone inversion layer so as to improve line roughness characteristics of the process. More specifically, a tone inversion layer may be patterned and then sidewalls of the tone inversion layer may be treated. A fill material may then be deposited upon the substrate including adjacent the sidewalls of the tone inversion layer. When the tone inversion layer is removed, the roughness of the fill material will be reduced due to the use of the sidewall treatment.

A superstrate for planarizing a substrate. The superstrate includes a body having a first side having a contact surface and a second side having a central portion and a peripheral portion surrounding the central portion. The peripheral portion includes a recessed region.

A device includes a substrate, a gate structure over the substrate, gate spacers on opposite sidewalls of the gate structure, source/drain structures over the substrate and on opposite sides of the gate structure, and a self-assemble monolayer (SAM) in contact with an inner sidewall of one of the gate spacer and in contact with a top surface of the gate structure.

A method for forming a planarization layer includes: providing a substrate including a trench; coating a pre-thinner over a surface of the trench; forming a gap-filling material in the trench; coating a post-thinner over the gap-filling material; and performing a spinning process to rotate the substrate.

Discussed generally herein are methods and devices including or providing a redistribution layer device without under ball metallization. A device can include a substrate, electrical interconnect circuitry in the substrate, redistribution layer (RDL) circuitry electrically connected to the electrical interconnect circuitry, a conductive bump electrically connected to the RDL circuitry, the conductive bump interfacing directly with the RDL circuitry, and a sheet molding material over the substrate.

Methods of curing polyimide to tune the coefficient of thermal expansion are provided herein. In some embodiments, a method of curing a polymer layer on a substrate, includes: (a) applying a variable frequency microwave energy to the substrate to heat the polymer layer and the substrate to a first temperature; and (b) adjusting the variable frequency microwave energy to increase a temperature of the polymer layer and the substrate to a second temperature to cure the polymer layer.

A semiconductor device structure is provided. The device includes a dielectric layer over a substrate. The substrate has a fin structure, and the dielectric layer has a trench exposing a portion of the fin structure. The includes a gate material layer in the trench. The gate material has a topmost surface that is highly planar.