A method includes depositing an interlayer dielectric (ILD) over a source/drain region, implanting impurities into a portion of the ILD, recessing the portion of the ILD to form a trench, forming spacers on sidewalls of the trench, the spacers including a spacer material, forming a source/drain contact in the trench and removing the spacers and the portion of the ILD with an etching process to form an air-gap, the air-gap disposed under and along sidewalls of the source/drain contact, where the etching process selectively etches the spacer material and the impurity.

A method for reducing wiggling in a line includes forming a silicon patterning layer over a substrate and depositing a mask layer over the silicon patterning layer. The mask layer is patterned to form one or more openings therein. The mask layer is thinned and the one or more openings are widened, to provide a smaller height-to-width ratio. The pattern of the mask layer is then used to pattern the silicon patterning layer. The silicon patterning layer is used, in turn, to pattern a target layer where a metal line will be formed.

There is provided resist underlayer film for lithography process with high dry etching resistance, wiggling resistance, and heat resistance. Resist underlayer film-forming composition for lithography including polymer having unit structure of Formula (1): wherein A is hydroxy group-substituted C.sub.6-40 arylene group derived from polyhydroxy aromatic compound; B is C.sub.6-40 arylene group or C.sub.4-30 heterocyclic group containing nitrogen atom, oxygen atom, sulfur atom, or combination thereof; X.sup.+ is H.sup.+, NH.sub.4.sup.+, primary ammonium ion, secondary ammonium ion, tertiary ammonium ion, or quaternary ammonium ion, T is hydrogen atom, C.sub.1-10 alkyl group or C.sub.6-40 aryl group that may be substituted with halogen group, hydroxy group, nitro group, amino group, carboxylate ester group, nitrile group, or combination thereof as substituent, or C.sub.4-30 heterocyclic group containing nitrogen atom, oxygen atom, sulfur atom, or combination thereof, B and T may form C.sub.4-40 ring together with carbon atom to which they are bonded. ##STR00001##

An etching method includes a step of selectively forming deposit on a top surface of a mask disposed on a film of a substrate, a step of etching the film after the step of forming the deposit, a step of forming a layer of chemical species included in plasma of a processing gas, on the substrate, and a step of supplying ions from plasma of an inert gas to the substrate so that the chemical species react with the film.

In a method of manufacturing a photo mask used in a semiconductor manufacturing process, a mask pattern layout in which a plurality of patterns are arranged is acquired. The plurality of patterns are converted into a graph having nodes and links. It is determined whether the nodes are colorable by N colors without causing adjacent nodes connected by a link to be colored by a same color, where N is an integer equal to or more than 3. When it is determined that the nodes are colorable by N colors, the nodes are colored with the N colors. The plurality of patterns are classified into N groups based on the N colored nodes. The N groups are assigned to N photo masks. N data sets for the N photo masks are output.

A control gate electrode and a memory gate electrode of a memory cell of a non-volatile memory are formed in a memory cell region of a semiconductor substrate, and a dummy gate electrode is formed in a peripheral circuit region. Then, n.sup.+-type semiconductor regions for a source or a drain of the memory cell are formed in the memory cell region and n.sup.+-type semiconductor regions for a source or a drain of MISFET are formed in the peripheral circuit region. Then, a metal silicide layer is formed over the n.sup.+-type semiconductor regions but the metal silicide layer is not formed over the control gate electrode, the memory gate electrode, and the gate electrode. Subsequently, the gate electrode is removed and replaced with the gate electrode for MISFET, Then, after removing the gate electrode and replacing it with a gate electrode for MISFET, a metal silicide layer is formed over the memory gate electrode and the control gate electrode.

Technologies for selectively etching oxide and nitride materials on a work piece are described. Such technologies include methods for etching a work piece with a remote plasma that is produced by igniting a plasma gas flow. By controlling the flow rate of various components of the plasma gas flow, plasmas exhibiting desired etching characteristics may be obtained. Such plasmas may be used in single or multistep etching operations, such as recess etching operations that may be used in the production of non-planar microelectronic devices.

The disclosed subject matter provides a semiconductor structure and fabrication method thereof. In a semiconductor structure, a dielectric layer, a plurality of discrete gate structures, and a plurality of sidewall spacers are formed on a semiconductor substrate. The plurality of discrete gate structures and sidewall spacers are formed in the dielectric layer, and a sidewall spacer is formed on each side of each gate structure. A top portion of each gate structure and a top portion of the dielectric layer between neighboring sidewall spacers of neighboring gate structures are removed. A protective layer is formed on each of the remaining dielectric layer and the remaining gate structures. Contact holes are formed on the semiconductor substrate, between neighboring sidewall spacers, and on opposite sides of the protective layer on the remaining dielectric layer. A metal plug is formed in each contact hole.

A manufacturing method for insulation layer, a manufacturing method for array substrate and an array substrate are disclosed. Wherein, the manufacturing method for insulation layer comprises steps of: depositing an insulation layer on a substrate; exposing and developing the insulation layer in order to obtain the insulation layer having an opening; light curing the insulation layer having the opening; and performing a high-temperature annealing treatment to the insulation layer having the opening after being light cured. Adopting the manufacturing method for insulation layer of the present invention, a situation of deformation at the opening of the insulation layer can be reduced.

Provided are an air up type transistor which has high electrical connection reliability and high productivity, and is capable of exhibiting good transistor characteristics while achieving microfabrication, and a manufacturing method of a transistor. A semiconductor layer is formed on an upper surface of a support precursor layer which becomes a semiconductor layer support and then a part of the semiconductor layer is removed to form one or more opening portions from which the support precursor layer is exposed. Two etching protective layers are formed on the semiconductor layer such that the two etching protective layers are separated from each other and at least a part of the opening portion is positioned in a region between the two etching protective layers. A part of the support precursor layer is removed by bringing an etchant into contact with the support precursor layer through the plurality of opening portions, thereby forming a space at a position corresponding to a region between the two etching protective layers so as to form two semiconductor layer supports that are arranged with the space interposed therebetween.