A method includes forming a fin structure over a substrate; forming a gate structure over the substrate and crossing the fin structure, wherein the gate structures comprises a gate electrode and a hard mask layer over the gate electrode; forming gate spacers on opposite sidewalls of the gate structure; performing an ion implantation process to form doped regions in the hard mask layers of the gate structure and in the gate spacers, wherein the ion implantation process is performed at a tilt angle; etching portions of the fin structure exposed by the gate structure and the gate spacers to form recesses in the fin structure; and forming source/drain epitaxial structures in the recesses.

Embodiments disclosed herein generally related to system for forming a semiconductor structure. The processing chamber includes a chamber body, a substrate support device, a quartz envelope, one or more heating devices, a gas injection assembly, and a pump device. The chamber body defines an interior volume. The substrate support device is configured to support one or more substrates during processing. The quartz envelope is disposed in the processing chamber. The quartz envelope is configured to house the substrate support device. The heating devices are disposed about the quartz envelope. The gas injection assembly is coupled to the processing chamber. The gas injection assembly is configured to provide an NH.sub.3 gas to the interior volume of the processing chamber. The pump device is coupled to the processing chamber. The pump device is configured to maintain the processing chamber at a pressure of at least 10 atm.

A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming an interfacial oxide layer on the fin structure, forming a first dielectric layer over the interfacial oxide layer, forming a dipole layer between the interfacial oxide layer and the first dielectric layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The dipole layer includes ions of first and second metals that are different from each other. The first and second metals have electronegativity values greater than an electronegativity value of a metal or a semiconductor of the first dielectric layer.

A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming an interfacial oxide layer on the fin structure, forming a first dielectric layer over the interfacial oxide layer, forming a dipole layer between the interfacial oxide layer and the first dielectric layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The dipole layer includes ions of first and second metals that are different from each other. The first and second metals have electronegativity values greater than an electronegativity value of a metal or a semiconductor of the first dielectric layer.

A process for depositing doped aluminum nitride (doped AlN) is disclosed. The process comprises subjecting a substrate to temporally separated exposures to an aluminum precursor and a nitrogen precursor to form an aluminum and nitrogen-containing compound on the substrate. The aluminum and nitrogen-containing compound is subsequently exposed to a dopant precursor to form doped AlN. The temporally separated exposures to an aluminum precursor and a nitrogen precursor, and the subsequent exposure to a dopant precursor together constitute a doped AlN deposition cycle. A plurality of doped AlN deposition cycles may be performed to deposit a doped AlN film of a desired thickness. The dopant content of the doped AlN can be tuned by performing a particular ratio of 1) separated exposures to an aluminum precursor and a nitrogen precursor, to 2) subsequent exposures to the dopant. The deposition may be performed in a batch process chamber, which may accommodate batches of 25 or more substrates. The deposition may be performed without exposure to plasma.

A process for depositing doped aluminum nitride (doped AlN) is disclosed. The process comprises subjecting a substrate to temporally separated exposures to an aluminum precursor and a nitrogen precursor to form an aluminum and nitrogen-containing compound on the substrate. The aluminum and nitrogen-containing compound is subsequently exposed to a dopant precursor to form doped AlN. The temporally separated exposures to an aluminum precursor and a nitrogen precursor, and the subsequent exposure to a dopant precursor together constitute a doped AlN deposition cycle. A plurality of doped AlN deposition cycles may be performed to deposit a doped AlN film of a desired thickness. The dopant content of the doped AlN can be tuned by performing a particular ratio of 1) separated exposures to an aluminum precursor and a nitrogen precursor, to 2) subsequent exposures to the dopant. The deposition may be performed in a batch process chamber, which may accommodate batches of 25 or more substrates. The deposition may be performed without exposure to plasma.

Semiconductor devices and methods which utilize a passivation dopant to passivate a gate dielectric layer are provided. The passivation dopant is introduced to the gate dielectric layer through a work function layer using a process such as a soaking method. The passivation dopant is an atom which may help to passivate electrical trapping defects, such as fluorine.

Semiconductor devices and methods which utilize a passivation dopant to passivate a gate dielectric layer are provided. The passivation dopant is introduced to the gate dielectric layer through a work function layer using a process such as a soaking method. The passivation dopant is an atom which may help to passivate electrical trapping defects, such as fluorine.

A method is provided for producing at least one first transistor and at least one second transistor on the same substrate, including producing at least one first gate pattern and at least one second gate pattern on the substrate; depositing at least one first protective layer on the first and the second gate patterns; depositing, on the first and the second gate patterns, at least a first protective layer and a second protective layer overlying, the first protective layer, the second protective layer being made from a different material than that of the first protective layer; masking the second gate pattern by a masking layer; isotropic etching of the second protective layer; removing the masking layer; and anisotropic etching of the second protective layer selectively relative to the first protective layer.

Methods and structures formed thereby are described relating to the doping non-planar fin structures. An embodiment of a structure includes a substrate, wherein the substrate comprises silicon, a fin on the substrate comprising a first portion and a second portion; and a dopant species, wherein the first portion comprises a first dopant species concentration, and the second portion comprises a second dopant species concentration, wherein the first dopant species concentration is substantially less than the second dopant species concentration.