Embodiments described herein relate to a method for patterning a doping layer, such as a lanthanum containing layer, used to dope a high-k dielectric layer in a gate stack of a FinFET device for threshold voltage tuning. A blocking layer may be formed between the doping layer and a hard mask layer used to pattern the doping layer. In an embodiment, the blocking layer may include or be aluminum oxide (AlO.sub.x). The blocking layer can prevent elements from the hard mask layer from diffusing into the doping layer, and thus, can improve reliability of the devices formed. The blocking layer can also improve a patterning process by reducing patterning induced defects.

A method for processing an integrated circuit includes forming I/O gate all around transistors and core gate all around transistors. The method performs a regrowth process on an interfacial gate dielectric layer of the I/O gate all around transistors by diffusing metal atoms into the interfacial dielectric layer I/O gate all around transistor. The regrowth process does not diffuse metal atoms into the interfacial gate dielectric layer of the gate all around core transistor.

A method for forming a semiconductor device structure is provided. The semiconductor device includes forming nanowire structures stacked over a substrate and spaced apart from one another, and forming a dielectric material surrounding the nanowire structures. The dielectric material has a first nitrogen concentration. The method also includes treating the dielectric material to form a treated portion. The treated portion of the dielectric material has a second nitrogen concentration that is greater than the first nitrogen concentration. The method also includes removing the treating portion of the dielectric material, thereby remaining an untreated portion of the dielectric material as inner spacer layers; and forming the gate stack surrounding nanowire structures and between the inner spacer layers.

The present disclosure provides a method for fabricating a semiconductor structure, including forming a dielectric layer over a first region and a second region of a substrate, wherein the second region is adjacent to the first region, increasing a thickness of the dielectric layer in the first region, including forming an oxygen capturing layer over the dielectric layer in the first region, including forming the oxygen capturing layer over the first region and the second region, and removing the oxygen capturing layer over the second region with a mask layer, performing an oxidizing operation from a top surface of the oxygen capturing layer to increase oxygen concentration of the oxygen capturing layer, removing the oxygen capturing layer over the first region, and forming a gate structure over the dielectric layer.

The present disclosure provides a method for fabricating a semiconductor structure, including forming a dielectric layer over a first region and a second region of a substrate, wherein the second region is adjacent to the first region, increasing a thickness of the dielectric layer in the first region, including forming an oxygen capturing layer over the dielectric layer in the first region, including forming the oxygen capturing layer over the first region and the second region, and removing the oxygen capturing layer over the second region with a mask layer, performing an oxidizing operation from a top surface of the oxygen capturing layer to increase oxygen concentration of the oxygen capturing layer, removing the oxygen capturing layer over the first region, and forming a gate structure over the dielectric layer.

There is provided a method of processing an oxygen-containing workpiece. The method of processing an oxygen-containing workpiece includes controlling a fluorine concentration in the oxygen-containing workpiece based on at least one of a kind of a fluorine-containing processing gas, a processing temperature and a processing pressure used for processing the oxygen-containing workpiece.

There is provided a method of processing an oxygen-containing workpiece. The method of processing an oxygen-containing workpiece includes controlling a fluorine concentration in the oxygen-containing workpiece based on at least one of a kind of a fluorine-containing processing gas, a processing temperature and a processing pressure used for processing the oxygen-containing workpiece.

In an embodiment, a device includes: a gate structure on a channel region of a substrate; a gate mask on the gate structure, the gate mask including a first dielectric material and an impurity, a concentration of the impurity in the gate mask decreasing in a direction extending from an upper region of the gate mask to a lower region of the gate mask; a gate spacer on sidewalls of the gate mask and the gate structure, the gate spacer including the first dielectric material and the impurity, a concentration of the impurity in the gate spacer decreasing in a direction extending from an upper region of the gate spacer to a lower region of the gate spacer; and a source/drain region adjoining the gate spacer and the channel region.

Semiconductor devices and methods of manufacturing semiconductor devices are described herein. A method includes implanting neutral elements into a dielectric layer, an etch stop layer, and a metal feature, the dielectric layer being disposed over the etch stop layer and the metal feature being disposed through the dielectric layer and the etch stop layer. The method further includes using a germanium gas as a source for the neutral elements and using a beam current above 6.75 mA to implant the neutral elements.

In a gate last metal gate process for forming a transistor, a dielectric layer is formed over an intermediate transistor structure, the intermediate structure including a dummy gate electrode, typically formed of polysilicon. Various processes, such as patterning the polysilicon, planarizing top layers of the structure, and the like can remove top portions of the dielectric layer, which can result in decreased control of gate height when a metal gate is formed in place of the dummy gate electrode, decreased control of fin height for finFETs, and the like. Increasing the resistance of the dielectric layer to attack from these processes, such as by implanting silicon or the like into the dielectric layer before such other processes are performed, results in less removal of the top surface, and hence improved control of the resulting structure dimensions and performance.