Techniques for tight pitch patterning are provided. In one aspect, a patterning method includes: forming mandrels on a substrate; forming spacers that are undoped alongside the mandrels, wherein gaps are present between the spacers; filling the gaps with a sacrificial material having a dopant; forming a mask having an opening marking a cut region of at least one of the spacers; removing the sacrificial material from the cut region of the at least one spacer via the mask; removing the mask; performing an anneal to diffuse the dopant from the sacrificial material into the spacers to form doped spacers, wherein following the anneal the cut region of the at least one spacer remains undoped; removing the cut region of the at least one spacer selective to the doped spacers; and patterning features in the substrate using the doped spacers as a hardmask. A patterning structure is also provided.

There is provided a technique that includes (a) forming a first film on the substrate by supplying a film-forming agent to the substrate; (b) adding oxygen to the first film by supplying a first oxidizing agent to the substrate and oxidizing a part of the first film; and (c) changing the oxygen-added first film into a second film including an oxide film by supplying a second oxidizing agent to the substrate and oxidizing the oxygen-added first film.

Methods and techniques for deposition of amorphous carbon films on a substrate are provided. In one example, the method includes depositing an amorphous carbon film on an underlayer positioned on a susceptor in a first processing region. The method further includes implanting a dopant or the inert species into the amorphous carbon film in a second processing region. The implant species, energy, dose & temperature in some combination may be used to enhance the hardmask hardness. The method further includes patterning the doped amorphous carbon film. The method further includes etching the underlayer.

A fin field effect transistor (Fin FET) device includes a fin structure extending in a first direction and protruding from an isolation insulating layer disposed over a substrate. The fin structure includes a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. The Fin FET device includes a gate structure covering a portion of the fin structure and extending in a second direction perpendicular to the first direction. The Fin FET device includes a source and a drain. Each of the source and drain includes a stressor layer disposed in recessed portions formed in the fin structure. The stressor layer extends above the recessed portions and applies a stress to a channel layer of the fin structure under the gate structure. The Fin FET device includes a dielectric layer formed in contact with the oxide layer and the stressor layer in the recessed portions.

A fin field effect transistor (Fin FET) device includes a fin structure extending in a first direction and protruding from an isolation insulating layer disposed over a substrate. The fin structure includes a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. The Fin FET device includes a gate structure covering a portion of the fin structure and extending in a second direction perpendicular to the first direction. The Fin FET device includes a source and a drain. Each of the source and drain includes a stressor layer disposed in recessed portions formed in the fin structure. The stressor layer extends above the recessed portions and applies a stress to a channel layer of the fin structure under the gate structure. The Fin FET device includes a dielectric layer formed in contact with the oxide layer and the stressor layer in the recessed portions.

A method for forming a semiconductor device structure is provided. The method includes forming a first semiconductor layer, an insulating layer and a second semiconductor layer in a substrate. The method also includes forming a first isolation feature in the first semiconductor layer, the insulating layer and the second semiconductor layer. The method further includes forming a transistor in and over the substrate adjacent to the first isolation feature. In addition, the method includes etching the first isolation feature to form a trench extending below the insulating layer. The method also includes filling the trench with a metal material to form a second isolation feature in the first isolation feature.

A method for forming a semiconductor device structure is provided. The method includes forming a first semiconductor layer, an insulating layer and a second semiconductor layer in a substrate. The method also includes forming a first isolation feature in the first semiconductor layer, the insulating layer and the second semiconductor layer. The method further includes forming a transistor in and over the substrate adjacent to the first isolation feature. In addition, the method includes etching the first isolation feature to form a trench extending below the insulating layer. The method also includes filling the trench with a metal material to form a second isolation feature in the first isolation feature.

In an embodiment, a structure includes: a nano-structure; an epitaxial source/drain region adjacent the nano-structure; a gate dielectric wrapped around the nano-structure; a gate electrode over the gate dielectric, the gate electrode having an upper portion and a lower portion, a first width of the upper portion increasing continually in a first direction extending away from a top surface of the nano-structure, a second width of the lower portion being constant along the first direction; and a gate spacer between the gate dielectric and the epitaxial source/drain region.

A method for forming spacers of a gate of a transistor is provided, including: providing an active layer surmounted by a gate; forming a dielectric layer covering the gate and the active layer, the dielectric layer having lateral portions, and basal portions covering the active layer; anisotropically modifying the basal portions by implantation of hydrogen-based ions in a direction parallel to the lateral sides of the gate, forming modified basal portions; annealing desorbing the hydrogen from the active layer and transforming the modified basal portions into second modified basal portions; and removing the modified basal portions by selective etching of the modified dielectric material with respect to the non-modified dielectric material and with respect to the semiconductive material, so as to form the spacers on the lateral sides of the gate.

A method includes forming a plurality of nanostructures over a substrate; etching the plurality of nanostructures to form recesses; forming source/drain regions in the recesses; removing first nanostructures of the plurality of nanostructures leaving second nanostructures of the plurality of nanostructures; depositing a gate dielectric over and around the second nano structures; depositing a protective material over the gate dielectric; performing a fluorine treatment on the protective material; removing the protective material; and depositing a first conductive material over the gate dielectric; and depositing a second conductive material over the first conductive material.