Semiconductor devices and methods of manufacturing the semiconductor devices are disclosed herein. The methods include forming nanostructures in a multilayer stack of semiconductor materials. An interlayer dielectric is formed surrounding the nanostructures and a gate dielectric is formed surrounding the interlayer dielectric. A first work function layer is formed over the gate dielectric. Once the first work function layer has been formed, an annealing process is performed on the resulting structure and oxygen is diffused from the gate dielectric into the interlayer dielectric. After performing the annealing process, a second work function layer is formed adjacent the first work function layer. A gate electrode stack of a nano-FET device is formed over the nanostructures by depositing a conductive fill material over the second work function layer.

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, first and second fin structures formed over the substrate, and an isolation structure between the first and second fin structures. The isolation structure can include a lower portion and an upper portion. The lower portion of the isolation structure can include a metal-free dielectric material. The upper portion of the isolation structure can include a metallic element and silicon.

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, first and second fin structures formed over the substrate, and an isolation structure between the first and second fin structures. The isolation structure can include a lower portion and an upper portion. The lower portion of the isolation structure can include a metal-free dielectric material. The upper portion of the isolation structure can include a metallic element and silicon.

A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes multiple semiconductor nanostructures over a substrate and two epitaxial structures over the substrate. Each of the semiconductor nanostructures is between the epitaxial structures, and the epitaxial structures are p-type doped. The semiconductor device structure also includes a gate stack wrapping around the semiconductor nanostructures. The semiconductor device structure further includes a dielectric stressor structure between the gate stack and the substrate. The epitaxial structures extend exceeding a top surface of the dielectric stressor structure.

A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.

According to one or more embodiments, a method for manufacturing a semiconductor device comprises forming a stacked film that comprises alternating first insulating layers and second insulating layers. A first insulating film, an electric charge storage layer, a second insulating film, and a first semiconductor layer are then formed in a hole in the stacked film. The method further includes forming a first recess in the stacked film, then supplying a first gas and a deuterium gas to the first recess. The first gas comprises hydrogen and oxygen.

Embodiments include nanostructure devices and methods of forming nanostructure devices which include a treatment process to expand a sidewall spacer material to close a seam in the sidewall spacer material after deposition. The treatment process includes oxygen plasma treatment to expand the sidewall spacer material and crosslink the open seam to form a closed seam, lower k-value, and decrease density.

A semiconductor device with low parasitic capacitance is provided. The semiconductor device includes a first oxide insulator, an oxide semiconductor, a second oxide insulator, a gate insulating layer, a gate electrode layer, source and drain electrode layers and an insulating layer. The oxide semiconductor includes first to fifth regions. The first region overlaps with the source electrode layer. The second region overlaps with the drain electrode layer. The third region overlaps with the gate electrode layer. The fourth region is between the first region and the third region. The fifth region is between the second region and the third region. The fourth region and the fifth region each contain an element N (N is hydrogen, nitrogen, helium, neon, argon, krypton, or xenon). A top surface of the insulating layer is positioned at a lower level than top surfaces of the source and drain electrode layers.

In an embodiment, a method includes: forming a gate dielectric layer on a channel region of a semiconductor feature; depositing a work function tuning layer on the gate dielectric layer, the work function tuning layer including a first work function tuning element; depositing a capping layer on the work function tuning layer with atomic layer deposition, the capping layer formed of an oxide or a nitride; performing an anneal process while the capping layer covers the work function tuning layer, the anneal process driving the first work function tuning element from the work function tuning layer into the gate dielectric layer; removing the capping layer to expose the work function tuning layer; and depositing a fill layer on the work function tuning layer.

Methods and techniques for deposition of amorphous carbon films on a substrate are provided. In one example, the method includes depositing an amorphous carbon film on an underlayer positioned on a susceptor in a first processing region. The method further includes implanting a dopant or the inert species into the amorphous carbon film in a second processing region. The implant species, energy, dose & temperature in some combination may be used to enhance the hardmask hardness. The method further includes patterning the doped amorphous carbon film. The method further includes etching the underlayer.