In accordance with embodiments of the present disclosure, an integrated circuit may include at least one region of shallow-trench isolation field oxide, at least one region of dummy diffusion, and a polycrystalline semiconductor resistor. The at least one region of shallow-trench isolation field oxide may be formed on a semiconductor substrate. The at least one region of dummy diffusion may be formed adjacent to the at least one region of shallow-trench isolation field oxide on the semiconductor substrate. The polycrystalline semiconductor resistor may comprise at least one resistor arm formed with a polycrystalline semiconductor material, wherein the at least one resistor arm is formed over each of the at least one region of shallow-trench isolation field oxide and the at least one region of dummy diffusion.

A method for manufacturing a semiconductor device is provided. In the method, a silicon-containing gas is supplied to a substrate having a recess in a surface thereof at a predetermined film deposition temperature, thereby depositing a first silicon film in the recess. Chlorine and hydrogen are supplied to the substrate while maintaining the predetermined film deposition temperature, thereby etching the first silicon film deposited in the recess to expand an opening width of the first silicon film. The silicon-containing gas is supplied to the substrate while maintaining the predetermined film deposition temperature, thereby further depositing a second silicon film on the first silicon film in the recess.

Methods for gap filling features of a substrate surface are described. Each of the features extends a distance into the substrate from the substrate surface and have a bottom and at least one sidewall. The methods include depositing a non-conformal film in the feature of the substrate surface with a plurality of high-frequency ratio-frequency (HFRF) pulses. The non-conformal film has a greater thickness on the bottom of the features than on the at least one sidewall. The deposited film is substantially etched from the sidewalls of the feature. The deposition and etch processes are repeated to fill the features.

A film forming method includes: removing a natural oxide film formed on a front surface of a metal-containing film by supplying a hydrogen fluoride gas to a substrate accommodated in a processing container, the substrate having the metal-containing film formed thereon, and the metal-containing film including no metal oxide film; and forming a silicon film on the metal-containing film by supplying a silicon-containing gas into the processing container, wherein the step of forming the silicon film occurs after the step of removing the natural oxide film.

A method for manufacturing a semiconductor device is provided. In the method, an amorphous silicon film is deposited in a recess provided in a surface of a substrate by supplying a silicon-containing gas to the substrate. The amorphous silicon film is etched by supplying an etching gas to the substrate so as to leave the amorphous silicon film on a bottom of the recess. A silicon film is deposited on the amorphous silicon film by supplying dichlorosilane to the substrate.

Embodiments of the present disclosure relate to processes for filling trenches. The process includes depositing a first amorphous silicon layer on a surface of a layer and a second amorphous silicon layer in a portion of a trench formed in the layer, and portions of side walls of the trench are exposed. The first amorphous silicon layer is removed. The process further includes depositing a third amorphous silicon layer on the surface of the layer and a fourth amorphous silicon layer on the second amorphous silicon layer. The third amorphous silicon layer is removed. The deposition/removal cyclic processes may be repeated until the trench is filled with amorphous silicon layers. The amorphous silicon layers form a seamless amorphous silicon gap fill in the trench since the amorphous silicon layers are formed from bottom up.

A method for forming a device includes forming a hole pattern in a resist layer disposed over a substrate. The substrate includes contact regions disposed over a major surface of the substrate and a dielectric layer disposed over the contact regions. The resist layer is disposed over the dielectric layer and the hole pattern includes through openings in the resist layer that are aligned with the contact regions. The through openings include a first through opening having a first critical dimension and a second through opening having a second critical dimension greater than the first critical dimension. The method includes modifying the hole pattern by depositing a material including silicon within the through openings by exposing the hole pattern to a first plasma generated from a gas mixture including SiCl.sub.4 and hydrogen, and then etching holes in the dielectric layer through the modified hole pattern, exposing the contact regions.

A method includes depositing a silicon layer, which includes first portions over a plurality of strips, and second portions filled into trenches between the plurality of strips. The plurality of strips protrudes higher than a base structure. The method further includes performing an anneal to allow parts of the first portions of the silicon layer to migrate toward lower parts of the plurality of trenches, and performing an etching on the silicon layer to remove some portions of the silicon layer.

A memory device and a method for fabricating the memory device are provided. The memory device includes a substrate having an upper surface; a stacked structure disposed on the upper surface of the substrate, wherein the stacked structure includes a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer and a third insulating layer sequentially stacked on the substrate; a plurality of channel structures penetrating the stacked structure and electrically connected to the substrate, wherein each of the channel structures includes an upper portion corresponding to the second conductive layer and a lower portion corresponding to the first conductive layer; a memory layer disposed between the second conductive layer and the upper portion; and a plurality of isolation structures penetrating the stacked structure to separate the stacked structure into a plurality of sub-stacks.

A method for forming a polycrystalline semiconductor layer includes forming a plurality of spacers over a dielectric layer, etching the dielectric layer using the plurality of spacers as an etch mask to form a recess in the dielectric layer, depositing an amorphous semiconductor layer over the plurality of spacers and the dielectric layer to fill the recess, and recrystallizing the amorphous semiconductor layer to form a polycrystalline semiconductor layer.