H01L21/321

SEMICONDUCTOR DEVICE WITH METAL NITRIDE LAYER AND A METHOD OF MANUFACTURING THEREOF

A semiconductor device includes a semiconductor substrate and a metal nitride layer above the semiconductor substrate. The metal nitride layer forms at least one interface region with the semiconductor substrate. The at least one interface region includes a first portion of the semiconductor substrate, a first portion of the metal nitride layer, and an interface between the first portion of the semiconductor substrate and the first portion of the metal nitride layer. A concentration of nitrogen content at the first portion of the metal nitride layer is higher than a concentration of nitrogen content at a second portion, of the metal nitride layer, outside the interface region. A distribution of nitrogen content throughout the metal nitride layer may have a maximum concentration at the first portion of the metal nitride layer. Alternatively and/or additionally, a method for producing such a semiconductor device is provided herein.

SEMICONDUCTOR DEVICE WITH METAL NITRIDE LAYER AND A METHOD OF MANUFACTURING THEREOF

A semiconductor device includes a semiconductor substrate and a metal nitride layer above the semiconductor substrate. The metal nitride layer forms at least one interface region with the semiconductor substrate. The at least one interface region includes a first portion of the semiconductor substrate, a first portion of the metal nitride layer, and an interface between the first portion of the semiconductor substrate and the first portion of the metal nitride layer. A concentration of nitrogen content at the first portion of the metal nitride layer is higher than a concentration of nitrogen content at a second portion, of the metal nitride layer, outside the interface region. A distribution of nitrogen content throughout the metal nitride layer may have a maximum concentration at the first portion of the metal nitride layer. Alternatively and/or additionally, a method for producing such a semiconductor device is provided herein.

Slurry and polishing method
11566150 · 2023-01-31 · ·

A slurry containing abrasive grains and a liquid medium, the abrasive grains including first particles and second particles being in contact with the first particles, the first particles containing ceria, the first particles having a negative zeta potential, the second particles containing a hydroxide of a tetravalent metal element, and the second particles having a positive zeta potential.

Endpoint detection for chemical mechanical polishing based on spectrometry

A method of detecting a polishing endpoint includes storing a plurality of library spectra, measuring a sequence of spectra from the substrate in-situ during polishing, and for each measured spectrum of the sequence of spectra, finding a best matching library spectrum from the plurality of library spectra to generate a sequence of best matching library spectra. Each library spectrum has a stored associated value representing a degree of progress through a polishing process, and the stored associated value for the best matching library spectrum is determined for each best matching library spectrum to generate a sequence of values representing a progression of polishing of the substrate. The sequence of values is compared to a target value, and a polishing endpoint is triggered when the sequence of values reaches the target value.

High voltage polysilicon gate in high-K metal gate device

An integrated circuit device includes a plurality of metal gates each having a metal electrode and a high-κ dielectric and a plurality of polysilicon gates each having a polysilicon electrode and conventional (non high-κ) dielectrics. The polysilicon gates may have adaptations for operation as high voltage gates including thick dielectric layers and area greater than one μm.sup.2. Polysilicon gates with these adaptations may be operative with gate voltages of 10V or higher and may be used in embedded memory devices.

Direct-bonded LED arrays including optical elements configured to transmit optical signals from LED elements

Direct-bonded LED arrays and applications are provided. An example process fabricates a LED structure that includes coplanar electrical contacts for p-type and n-type semiconductors of the LED structure on a flat bonding interface surface of the LED structure. The coplanar electrical contacts of the flat bonding interface surface are direct-bonded to electrical contacts of a driver circuit for the LED structure. In a wafer-level process, micro-LED structures are fabricated on a first wafer, including coplanar electrical contacts for p-type and n-type semiconductors of the LED structures on the flat bonding interface surfaces of the wafer. At least the coplanar electrical contacts of the flat bonding interface are direct-bonded to electrical contacts of CMOS driver circuits on a second wafer. The process provides a transparent and flexible micro-LED array display, with each micro-LED structure having an illumination area approximately the size of a pixel or a smallest controllable element of an image represented on a high-resolution video display.

CHEMICAL MECHANICAL POLISHING SOLUTION
20230026568 · 2023-01-26 ·

Disclosed is a chemical mechanical polishing solution containing water, cerium oxide abrasive particles and hydroxylamine, which can also increase the removal rate of patterned silicon dioxide with further addition of 4-hydroxybenzoic acid or salicylhydroxamic acid.

CERIUM-BASED PARTICLE AND POLISHING SLURRY COMPOSITION INCLUDING THE SAME
20230025469 · 2023-01-26 · ·

Provided is a new cerium-based particle and a polishing slurry composition including the same. The new cerium-based particle may include a self-assembly of fine particles and an organic material.

METHOD OF MANUFACTURING BARRIER-METAL-FREE METAL INTERCONNECT STRUCTURE, AND BARRIER-METAL-FREE METAL INTERCONNECT STRUCTURE
20230230878 · 2023-07-20 · ·

The present invention relates to a metal interconnect structure containing no barrier metal and a method of manufacturing the metal interconnect structure. The method includes: filling at least a first interconnect trench with an intermetallic compound by depositing the intermetallic compound on an insulating layer having the first interconnect trench and a second interconnect trench formed in the insulating layer, the second interconnect trench being wider than the first interconnect trench; performing a planarization process of polishing the intermetallic compound until the insulating layer is exposed; and then performing a height adjustment process of polishing the intermetallic compound and the insulating layer until a height of the intermetallic compound in the first interconnect trench reaches a predetermined height.

ELECTRO-OXIDATIVE METAL REMOVAL ACCOMPANIED BY PARTICLE CONTAMINATION MITIGATION IN SEMICONDUCTOR PROCESSING

During electro-oxidative metal removal on a semiconductor substrate, the substrate having a metal layer is anodically biased and the metal is electrochemically dissolved into an electrolyte. Metal particles (e.g., copper particles when the dissolved metal is copper) can inadvertently form on the surface of the substrate during electrochemical metal removal and cause defects during subsequent semiconductor processing. Contamination with such particles can be mitigated by preventing particle formation and/or by dissolution of particles. In one implementation, mitigation involves using an electrolyte that includes an oxidizer, such as hydrogen peroxide, during the electrochemical metal removal. An electrochemical metal removal apparatus in one embodiment has a conduit for introducing an oxidizer to the electrolyte and a sensor for monitoring the concentration of the oxidizer in the electrolyte.