Integrated fan-out devices, wafer level packages, and methods of manufacturing the same are described herein. Die-attach pads and leveling film are used to attach a plurality of heterogeneous semiconductor dies to a substrate to align external contacts of the semiconductor dies at a first level. The leveling film may also be used during deposition of an encapsulant to at least partially fill a gap between the semiconductor dies. Once the leveling film is removed, a protection layer is formed over the semiconductor dies and within a recess of the encapsulant left behind by the leveling film during encapsulation. A redistribution layer and external connectors are formed over the protection layer to form the InFO device and an interposer may be attached to the redistribution layer to form the wafer level package.

The disclosure provides an electronic apparatus and a manufacturing method thereof. The electronic apparatus includes a first insulating layer, a first metal layer, a second metal layer, and an electronic assembly. The first insulating layer includes a first surface and a second surface opposite to the first surface. The first metal layer has an opening and is formed on the first surface. The second metal layer is formed on the second surface and a projection of the opening on the second surface is overlapped with a projection of the second metal layer on the second surface. The electronic assembly is electrically connected with the first metal layer and the second metal layer.

A method for manufacturing a semiconductor device includes preparing a temporary fixing structure body in which semiconductor elements each including a first surface on which a connection terminal is formed and a second surface are attached to a temporary fixing material, forming a curable bonding adhesive layer on the second surface of each of the semiconductor elements, attaching a carrier to one surface of the curable bonding adhesive layer opposite to the semiconductor elements, fixing the semiconductor elements to the carrier by curing the curable bonding adhesive layer, and removing the temporary fixing material. The semiconductor elements are attached onto the temporary fixing material such that the first surface of each of the semiconductor elements is directed toward the temporary fixing material, and are encapsulated with an encapsulant material such that the second surface of each of the semiconductor elements is exposed from an encapsulant material layer.

Embodiments relate to testing a plurality of LEDs by applying a voltage difference between anode electrodes and cathode electrodes of the plurality of LEDs using transistors and probe pads on a display substrate. The anode electrodes of the plurality of LEDs are connected to a first probe pad via clamping transistors, and the cathode electrodes are connected to a second probe pad. Responsive to applying the voltage difference, it is determined whether the plurality of LEDs satisfy a threshold level of operability. The display substrate also includes driving transistors and switching transistors connected to the plurality of LEDs, the driving transistors and switching transistors used during operating mode.

A method comprises embedding a semiconductor structure in a molding compound layer, depositing a plurality of photo-sensitive material layers over the molding compound layer, developing the plurality of photo-sensitive material layers to form a plurality of openings, wherein a first portion and a second portion of an opening of the plurality of openings are formed in different photo-sensitive material layers and filling the first portion and the second portion of the opening with a conductive material to form a first via in the first portion and a first redistribution layer in the second portion.

Embodiments relate to testing a plurality of LEDs by applying a voltage difference between anode electrodes and cathode electrodes of the plurality of LEDs using transistors and probe pads on a display substrate. The anode electrodes of the plurality of LEDs are connected to a first probe pad via clamping transistors, and the cathode electrodes are connected to a second probe pad. Responsive to applying the voltage difference, it is determined whether the plurality of LEDs satisfy a threshold level of operability. The display substrate also includes driving transistors and switching transistors connected to the plurality of LEDs, the driving transistors and switching transistors used during operating mode.

A method comprises embedding a semiconductor structure in a molding compound layer, depositing a plurality of photo-sensitive material layers over the molding compound layer, developing the plurality of photo-sensitive material layers to form a plurality of openings, wherein a first portion and a second portion of an opening of the plurality of openings are formed in different photo-sensitive material layers and filling the first portion and the second portion of the opening with a conductive material to form a first via in the first portion and a first redistribution layer in the second portion.

A multi-chip packaging method includes: flip-mounting a first chip on a substrate on which first metal posts are arranged; mold packaging the first metal posts and the first chip to obtain a first package; forming a first redistribution layer on the surface of the first package; flip-mounting a second chip on a surface of the first redistribution layer and mold packaging the second chip to obtain a second package; removing the substrate and forming a second redistribution layer on a surface of the first package; forming second metal posts spaced apart from each other and flip-mounting a third chip on a surface of the second redistribution layer, and mold packaging the third chip and the second metal posts to obtain a third package; forming solder balls on a surface of the third package, where the solder balls are electrically connected to the second redistribution layer through the second metal posts.

A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.

A chip package structure includes a redistribution layer, at least one chip, a reinforcing frame, an encapsulant and a plurality of solder balls. The redistribution layer includes a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the redistribution layer. The reinforcing frame is disposed on the first surface and includes at least one through cavity. The chip is disposed in the through cavity and a stiffness of the reinforcing frame is greater than a stiffness of the redistribution layer. The encapsulant encapsulates the chip, the reinforcing frame and covering the first surface. The solder balls are disposed on the second surface and electrically connected to the redistribution layer.