A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.

A method comprises embedding a semiconductor structure in a molding compound layer, depositing a plurality of photo-sensitive material layers over the molding compound layer, developing the plurality of photo-sensitive material layers to form a plurality of openings, wherein a first portion and a second portion of an opening of the plurality of openings are formed in different photo-sensitive material layers and filling the first portion and the second portion of the opening with a conductive material to form a first via in the first portion and a first redistribution layer in the second portion.

A Fin-FET device and its fabrication method are provided. The method for fabricating the Fin-FET device includes forming a plurality of fin structures on a substrate, forming an isolation film on the substrate between neighboring fin structures, removing a portion of the isolation film to form an initial isolation layer with a top surface of the initial isolation layer lower than top surfaces of the fin structures, and implanting doping ions into the initial isolation layer. Further, the method also includes removing a portion of the initial isolation layer to form an isolation layer.

The present disclosure, in some embodiments, relates to a semiconductor package. The semiconductor package includes an interposer substrate laterally surrounding through-substrate-vias. A redistribution structure is on a first surface of the interposer substrate. The redistribution structure laterally extends past an outermost sidewall of the interposer substrate. A packaged die is bonded to the redistribution structure. One or more conductive layers are arranged along a second surface of the interposer substrate opposite the first surface. A molding compound vertically extends from the redistribution structure to laterally surround the one or more conductive layers.

A chip package structure includes a substrate, a chip, an encapsulant, a plurality of solder balls and a patterned metal layer. The substrate includes a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the substrate. The encapsulant encapsulates the chip and covering the first surface. The solder balls are disposed on the second surface and electrically connected to the substrate. The patterned metal layer s disposed on the encapsulant. The patterned metal layer includes at least one concave portion and at least one convex portion defined by the concave portion. The convex portion faces the encapsulant. The adhesion layer is disposed between the patterned metal layer and the encapsulant. The adhesion layer is filled in the concave portion.

A device comprises a semiconductor structure in a molding compound layer, a first polymer layer on the molding compound layer, a second polymer layer on the first polymer layer, a first interconnect structure having a first via portion in the first polymer layer and a first metal line portion in the second polymer layer, a third polymer layer on the second polymer layer, a fourth polymer layer on the third polymer layer and a second interconnect structure having a second via portion in the third polymer layer and a second metal line portion in the fourth polymer layer, wherein the second via portion is vertically aligned with the first via portion.

A disclosed method for manufacturing an electronic-component-mounted substrate includes: a step (i) of forming a temporary fixing film 13 in such a manner as to cover a plurality of solder precoats (11) formed on a plurality of lands (10b) on a substrate and an antioxidation film (12) formed in such a manner as to cover the solder precoats; a step (ii) of disposing a plurality of electronic components (30) on the plurality of solder precoats (11) via the antioxidation film (12) and the temporary fixing film (13); and a step (iii) of soldering the plurality of electronic components (30) to the plurality of lands (10b) by melting the plurality of solder precoats (11). The antioxidation film (12) contains a first thermoplastic resin. The temporary fixing film (13) contains an activating agent and a second thermoplastic resin. The softening point of the second thermoplastic resin is equal to or lower than the softening point of the first thermoplastic resin.

A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.

A method is disclosed. In one example, the method comprises mounting an electronic component on an adhesive base structure on a temporary carrier, and dissolving at least part of the base structure by irradiating the base structure with electromagnetic radiation to thereby release the electronic component.

A device comprises a semiconductor structure in a molding compound layer, a first polymer layer on the molding compound layer, a second polymer layer on the first polymer layer, a first interconnect structure having a first via portion in the first polymer layer and a first metal line portion in the second polymer layer, a third polymer layer on the second polymer layer, a fourth polymer layer on the third polymer layer and a second interconnect structure having a second via portion in the third polymer layer and a second metal line portion in the fourth polymer layer, wherein the second via portion is vertically aligned with the first via portion.