Patent classifications
H
ELECTRICITY
Load children
H01
ELECTRIC ELEMENTS
Load children
H01L
SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
Load children
21/00
Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Load children Filter patents View analytics View as hierarchy Open in page
H01L21/02
Manufacture or treatment of semiconductor devices or of parts thereof
Load children Filter patents View analytics View as hierarchy Open in page
H01L21/04
the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
Load children Filter patents View analytics View as hierarchy Open in page
H01L21/50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07; e.g. sealing of a cap to a base of a container
Load children Filter patents View analytics View as hierarchy Open in page
H01L21/60
Attaching; or detaching; leads or other conductive members, to be used for carrying current to or from the device in operation
Load children Filter patents View analytics View as hierarchy Open in page
H01L2021/60007
involving a soldering or an alloying process
Load children Filter patents View analytics View as hierarchy Open in page
H01L2021/60022
using bump connectors, e.g. for flip chip mounting
Load children Filter patents View analytics View as hierarchy Open in page
H01L2021/60097
Applying energy, e.g. for the soldering or alloying process
Load children Filter patents View analytics View as hierarchy Open in page

H01L2021/60097

Vertically integrated wafers with thermal dissipation
09812428 · 2017-11-07 · ·

Technologies are generally described related to three-dimensional integration of integrated circuits (ICs) with spacing for heat dissipation. According to some examples, a self-aligned silicide may be formed in a temporary silicon layer and removed subsequent to bonding of the wafers to achieve improved contact between the combined ICs and enhanced heat dissipation through added spacing between the ICs.

VERTICALLY INTEGRATED WAFERS WITH THERMAL DISSIPATION
20170040295 · 2017-02-09 · ·

Technologies are generally described related to three-dimensional integration of integrated circuits (ICs) with spacing for heat dissipation. According to some examples, a self-aligned silicide may be formed in a temporary silicon layer and removed subsequent to bonding of the wafers to achieve improved contact between the combined ICs and enhanced heat dissipation through added spacing between the ICs.

TUNABLE LOW-COST PASSIVATION COATING FOR FACILITATING FLUXLESS BONDING OF COPPER SOLDER INTERCONNECTS IN FLIP CHIP ASSEMBLY
20250364276 · 2025-11-27 ·

The invention provides improved techniques for bonding copper to solder or other types of flip chip devices using a passivation coating on copper. The surface of a substrate is cleaned prior to mounting a flip chip device onto the substrate. The substrate is rinsed to remove residual artifacts remaining on the surface subsequent to the cleaning. Subsequent to the rinsing, a protective coating is applied to the surface of the substrate to produce a coated substrate. Copper pillars with solder caps extending from the flip chip device are bonded to metallic features on the surface of the coated substrate.