A silicon island structure and a method of fabricating same are disclosed. The method includes: forming multiple first trenches in a silicon substrate; forming second trenches by partially filling some of the first trenches with an insulating material; depositing a protective layer over the silicon substrate and over the second trenches; removing the protective layer over bottoms of the second trenches and the insulating material under the second trenches, thereby exposing sidewalls of some first trenches; oxidizing portions of the silicon substrate between the exposed sidewalls of the first trenches to form an oxide layer; removing the protective layer covering sidewalls of the second trenches; and filling the second trenches with an isolating material to form isolations, wherein portions of the silicon substrate between the isolations define silicon islands. This method enables the formation of silicon islands at desired locations with reduced process complexity and cost.

A power semiconductor device includes a semiconductor-on-insulator island having a semiconductor region and an insulation structure, the insulation structure being formed by an oxide and separating the semiconductor region from a portion of a semiconductor body of the power semiconductor device. The insulation structure includes a sidewall that laterally confines the semiconductor region; a bottom that vertically confines the semiconductor region; and a local deepening that forms at least a part of a transition between the sidewall and the bottom, wherein the local deepening extends further along the extension direction as compared to the bottom.

A power semiconductor device includes a semiconductor-on-insulator island having a semiconductor region and an insulation structure, the insulation structure being formed by an oxide and separating the semiconductor region from a portion of a semiconductor body of the power semiconductor device. The insulation structure includes a sidewall that laterally confines the semiconductor region; a bottom that vertically confines the semiconductor region; and a local deepening that forms at least a part of a transition between the sidewall and the bottom, wherein the local deepening extends further along the extension direction as compared to the bottom.

A curtain airbag device mounting structure includes: a first pillar forming a part of a front pillar and extends substantially along a vehicle height direction; a second pillar forming another part of the front pillar, the second pillar being disposed on a rear side of a vehicle relative to the first pillar at a predetermined distance from the first pillar and extending substantially along the vehicle height direction; a transparent member bridged between the first pillar and the second pillar; and a curtain airbag device including a curtain airbag stored along a roof side rail and the second pillar, the curtain airbag being configured to inflate and deploy in a curtain-like fashion over a side portion of a cabin of the vehicle in case of a collision of the vehicle.

An electronic device includes an isolated region surrounded by an isolation ring over a semiconductor substrate. A well of a first conductivity type is located within the isolated region. A source region and a drain region of a second conductivity type are located over the well. A local-oxidation-of-silicon (LOCOS) layer is located on the well between the source and the drain, between the source and the isolation ring, and between the drain and the isolation ring. A gate electrode located between the source and the drain on said LOCOS layer.

An integrated circuit (IC) including at least one transistor having a metal-oxide-semiconductor (MOS) gate includes a substrate having a semiconductor surface. The transistor includes at least one trench isolation region in the semiconductor surface. Local oxidation of silicon (LOCOS) regions extend from within the semiconductor surface inside the trench isolation region defining a first LOCOS-free region and at least a second LOCOS-free region. A gate electrode is between the first LOCOS-free region and second LOCOS-free region including over a flat portion of a first of the LOCOS regions as its gate dielectric (LOCOS gate oxide). A first doped region is in the first LOCOS-free region and a second doped region is in the second LOCOS-free region on respective sides of the gate electrode both doped a first dopant type. A recessed channel region for the transistor is between the first and second doped regions under the LOCOS gate oxide.

An integrated circuit (IC) including at least one transistor having a metal-oxide-semiconductor (MOS) gate includes a substrate having a semiconductor surface. The transistor includes at least one trench isolation region in the semiconductor surface. Local oxidation of silicon (LOCOS) regions extend from within the semiconductor surface inside the trench isolation region defining a first LOCOS-free region and at least a second LOCOS-free region. A gate electrode is between the first LOCOS-free region and second LOCOS-free region including over a flat portion of a first of the LOCOS regions as its gate dielectric (LOCOS gate oxide). A first doped region is in the first LOCOS-free region and a second doped region is in the second LOCOS-free region on respective sides of the gate electrode both doped a first dopant type. A recessed channel region for the transistor is between the first and second doped regions under the LOCOS gate oxide.

A method of forming a semiconductor device includes forming a plurality of trenches extending into a semiconductor substrate from a first surface of the semiconductor substrate. Each of the trenches includes a narrower part in open communication with a wider part that is spaced apart from the first surface by the narrower part. The narrower part of adjacent trenches is laterally separated by a first region of the semiconductor substrate. The wider part of adjacent trenches is laterally separated by a second region of the semiconductor substrate that is narrower than the first region. The method further includes introducing an oxidizing agent into the wider part of the trenches through the narrower part of the trenches to oxidize the second region of the semiconductor substrate between adjacent trenches to form dielectric support structures that support the first region of the semiconductor.

A semiconductor device includes first pillar-shaped semiconductor layers, a first gate insulating film formed around the first pillar-shaped semiconductor layers, gate electrodes formed around the first gate insulating film, gate lines connected to the gate electrodes, a second gate insulating film formed around upper portions of the first pillar-shaped semiconductor layers, first contacts formed of a first metal material and formed around the second gate insulating film, second contacts formed of a second metal material and connecting upper portions of the first contacts and upper portions of the first pillar-shaped semiconductor layers, diffusion layers formed in lower portions of the first pillar-shaped semiconductor layers, pillar-shaped insulator layers formed on the second contacts, variable-resistance films formed around upper portions of the pillar-shaped insulator layers, and lower electrodes formed around lower portions of the pillar-shaped insulator layers and connected to the variable-resistance films.

A power semiconductor device includes a semiconductor-on-insulator island having a semiconductor region and an insulation structure, the insulation structure being formed by an oxide and separating the semiconductor region from a portion of a semiconductor body of the power semiconductor device. The insulation structure includes a sidewall that laterally confines the semiconductor region; a bottom that vertically confines the semiconductor region; and a local deepening that forms at least a part of a transition between the sidewall and the bottom, wherein the local deepening extends further along the extension direction as compared to the bottom.