A method for making a high-voltage thick gate oxide, which includes depositing a pad silicon oxide on a silicon substrate and depositing a pad silicon nitride on the pad silicon oxide; performing shallow trench isolation photolithography, etching, silicon oxide filling and chemical mechanical polishing; sequentially depositing a mask silicon nitride and a mask silicon oxide on a silicon wafer; removing the mask silicon oxide and the mask silicon nitride in a high-voltage thick gate oxide region, and remaining the pad silicon nitride between two shallow trench isolations in the high-voltage thick gate oxide region; performing first thermal oxidation growth; removing the pad silicon nitride between the two shallow trench isolations in the high-voltage thick gate oxide region; performing second thermal oxidation growth to produce a high-voltage thick gate oxide.

Provided is a method for manufacturing a semiconductor device including: patterning a substrate to form a plurality of active patterns including two adjacent active patterns having a first trench therebetween; forming a semiconductor layer on the plurality of active patterns to cover the plurality of active patterns; forming a device isolation layer on the semiconductor layer to cover the semiconductor layer for oxidization and fill the first trench; patterning the device isolation layer and the plurality of active patterns so that a second trench intersecting the first trench is formed and the two active patterns protrudes from the device isolation layer in the second trench; and forming a gate electrode in the second trench. Here, a first thickness of the semiconductor layer covering a top surface of each of the two active patterns is greater than a second thickness of the semiconductor layer covering a bottom of the first trench.

Structures for shallow trench isolation regions and methods for forming shallow trench isolation regions. A trench is etched partially through a device layer of a silicon-on-insulator substrate. A section of the device layer at a bottom of the trench is thermally oxidized to form a shallow trench isolation region in the trench. During the thermal oxidation, another region of the device layer may be concurrently oxidized over a partial thickness and, after removal of the oxide from this device layer region, used as a thinned silicon body. Prior to the thermal oxidation process, this device layer region may be implanted with an oxidation-retarding species that decreases its oxidation rate in comparison with the oxidation rate of the section of the device layer used to form the shallow trench isolation region.

Structures for shallow trench isolation regions and methods for forming shallow trench isolation regions. A trench is etched partially through a device layer of a silicon-on-insulator substrate. A section of the device layer at a bottom of the trench is thermally oxidized to form a shallow trench isolation region in the trench. During the thermal oxidation, another region of the device layer may be concurrently oxidized over a partial thickness and, after removal of the oxide from this device layer region, used as a thinned silicon body. Prior to the thermal oxidation process, this device layer region may be implanted with an oxidation-retarding species that decreases its oxidation rate in comparison with the oxidation rate of the section of the device layer used to form the shallow trench isolation region.

A method for forming a trench in a first semiconductor layer of a multi-layer system. The method includes: applying a mask layer onto the first semiconductor layer, a recess being formed in the mask layer so that the first semiconductor layer is exposed within the recess; applying a protective layer which completely covers or modifies the first semiconductor layer exposed within the recess; applying a second semiconductor layer; etching the second semiconductor layer to completely remove it in a subarea surrounding the recess of the mask layer; etching the protective layer so that the first semiconductor layer is exposed within the recess; and forming the trench in the first semiconductor layer, the recess of the mask layer serving as an etching mask, and the trench being formed by a cyclical alternation between etching and passivation steps, the first etching step being longer than the subsequent etching steps.

A semiconductor device is provided. The semiconductor device includes a semiconductor layer, and a trench formed in a top surface of the semiconductor layer. The trench has a bottom surface and a sidewall. The semiconductor device further includes source and drain regions. One of the source and drain regions may be disposed at the bottom surface of the trench, and the other may be disposed at the top surface of the semiconductor layer, or vice versa. Alternatively, both source and drain regions may be disposed at the bottom surface of the trench. The semiconductor device may further include a first insulator disposed in the trench and in between the source and drain regions. The semiconductor device may further include a second insulator disposed between first insulator and the source region. The semiconductor device may further include a conductive member that disposed on the first insulator, or on the first and second insulators.

A semiconductor device is provided. The semiconductor device includes a semiconductor layer, and a trench formed in a top surface of the semiconductor layer. The trench has a bottom surface and a sidewall. The semiconductor device further includes source and drain regions. One of the source and drain regions may be disposed at the bottom surface of the trench, and the other may be disposed at the top surface of the semiconductor layer, or vice versa. Alternatively, both source and drain regions may be disposed at the bottom surface of the trench. The semiconductor device may further include a first insulator disposed in the trench and in between the source and drain regions. The semiconductor device may further include a second insulator disposed between first insulator and the source region. The semiconductor device may further include a conductive member that disposed on the first insulator, or on the first and second insulators.

A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate having multiple structures. Each of the structures includes an active region isolated by trenches in the substrate, an insulating layer on the active region, and a hardmask layer on the insulating layer. The method also includes performing a first ion implantation into a first structure configured to form a first type device, performing a pull-back process on the hardmask layer and on the insulating layer of the first structure to form a receded hardmask layer and a receded insulating layer and expose a corner portion of the active region, and performing a rounding process on the exposed corner portion. The rounded corner portion of the active region has an increased curvature radius that reduces the concentration of the electric field and improves the reliability of the semiconductor device.

A method for fabricating semiconductor device is disclosed. First, a substrate having a first region and a second region is provided, a shallow trench isolation (STI) is formed in the substrate to separate the first region and the second region, and a patterned hard mask is formed on the first region and part of the STI, in which the patterned hard mask exposes includes an opening to expose part of the STI. Next, a gas is driven-in through the exposed STI to alter an edge of the substrate on the first region.

A semiconductor structure includes a semiconductor substrate and a shallow trench isolation (STI). The STI includes a sidewall interfacing with the semiconductor substrate. The STI extrudes from a bottom portion of the semiconductor substrate, and the STI includes a bottom surface contacting the bottom portion of the semiconductor substrate; a top surface opposite to the bottom surface. The bottom surface includes a width greater than a width of the top surface.