A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between RF devices.

A method of forming a semiconductor device includes mounting a bottom wafer on a bottom chuck and mounting a top wafer on a top chuck, wherein one of the bottom chuck and the top chuck has a gasket. The top chuck is moved towards the bottom chuck. The gasket forms a sealed region between the bottom chuck and the top chuck around the top wafer and the bottom wafer. An ambient pressure in the sealed region is adjusted. The top wafer is bonded to the bottom wafer.

A method for transferring a semiconductor layer from a donor substrate to a receiver substrate having an open cavity includes forming an embrittlement plane in the donor substrate, making, by bringing the donor substrate and the receiver substrate into contact, a packaging in which the cavity is buried, and separating the packaging by fracturing along the embrittlement plane. The separating causes a transfer of the semiconductor layer to the receiver substrate and a sealing of the cavity by the semiconductor layer. The method also includes, prior to making the packaging, implanting diffusing species into the donor substrate or into the receiver substrate and, subsequently to making the packaging and prior to separating the packaging, diffusing the species into the cavity.

A layer transfer process comprises depositing a first, temporary bonding layer of SOG comprising methylsiloxane by spin coating on a surface comprising substantially no silicon of an initial substrate, and applying a first heat treatment for densifying the first, temporary bonding layer. An intermediate substrate is joined to the initial substrate, and then thinned A second bonding layer of SOG comprising silicate or methylsilsesquioxane is deposited by spin coating on a surface of the thinned initial substrate and/or a final substrate, and a second heat treatment is applied for densifying the second bonding layer. The thinned initial substrate and the final substrate and then joined, and the intermediate substrate is detached thereafter. The process may be carried out at temperatures below 300° C. to avoid damaging components that may be present in the substrates.

A semiconductor device is provided, which includes a multi-layered substrate having an interposed polymeric film and a device layer arranged over the multi-layered substrate.

A semiconductor structure for radio frequency applications includes a support substrate made of silicon and comprising a mesoporous layer, a dielectric layer arranged on the mesoporous layer and a superficial layer arranged on the dielectric layer. The mesoporous layer comprises hollow pores, the internal walls of which are mainly lined with oxide. The mesoporous layer has a thickness between 3 and 40 microns and a resistivity greater than 20 kohm.cm over its entire thickness. The support substrate has a resistivity between 0.5 and 4 ohm.cm. The invention also relates to a method for producing such a semiconductor structure.

A method for fabricating semiconductor chip structures, which comprises steps of: providing plural slice units tiled with one another on a process carrier, wherein each slice unit is made from a wafer and includes a substrate with an outline, and a gap is formed between adjacent two of the slice units; planarizing tops of the slice units; accomplishing circuits on the slice units and turning them into circuited slice units; and forming plural semiconductor chip structures individually with each other by at least breaking down the circuited slice units; wherein a planar size of one slice unit is no less than that of a corresponding semiconductor chip structure, or the planar size of one slice unit is no less than multiple of the planar size of the corresponding semiconductor chip structure. A semiconductor carrier and a semiconductor chip structure made by the method are also provided.

A method for manufacturing a bonded SOI wafer, the method using a silicon single crystal wafer having a resistivity of 100 Ω.Math.cm or more as the base wafer, and including steps of: forming an underlying insulator film on a bonding surface side of the base wafer; depositing a polycrystalline silicon layer on a surface of the underlying insulator film; polishing a surface of the polycrystalline silicon layer; modifying the polycrystalline silicon layer by performing ion implantation on the polished polycrystalline silicon layer to form a modified silicon layer; forming the insulator film on a bonding surface of the bond wafer; bonding the bond wafer and a surface of the modified silicon layer of the base wafer with the insulator film interposed therebetween; and thinning the bonded bond wafer to form an SOI layer. This provides a bonded SOI wafer excellent in harmonic wave characteristics.

A carrier configured to be attached to a semiconductor substrate via a first surface comprises a continuous carbon structure defining a first surface of the carrier, and a reinforcing material constituting at least 2 vol-% of the carrier.

A method for bonding a first substrate and a second substrate comprises bringing the first and second substrates into contact and implementing heating of a peripheral zone of at least one of the first and second substrates. The heating is initiated before the substrates are brought into contact and continued at least until the substrates are brought into contact in the zone. The heating is implemented by an infrared lamp configured to emit radiation having an outer boundary corresponding to the edge of the substrates.