METHOD FOR FABRICATING SEMICONDUCTOR CHIP STRUCTURES, SEMICONDUCTOR CARRIER AND SEMICONDUCTOR CHIP STRUCTURE

Abstract

A method for fabricating semiconductor chip structures, which comprises steps of: providing plural slice units tiled with one another on a process carrier, wherein each slice unit is made from a wafer and includes a substrate with an outline, and a gap is formed between adjacent two of the slice units; planarizing tops of the slice units; accomplishing circuits on the slice units and turning them into circuited slice units; and forming plural semiconductor chip structures individually with each other by at least breaking down the circuited slice units; wherein a planar size of one slice unit is no less than that of a corresponding semiconductor chip structure, or the planar size of one slice unit is no less than multiple of the planar size of the corresponding semiconductor chip structure. A semiconductor carrier and a semiconductor chip structure made by the method are also provided.

Claims

1. A method for fabricating semiconductor chip structures, comprising: providing a plurality of slice units tiled with one another on a surface of a process carrier, wherein each of the slice units is made by a wafer and includes a substrate with an outline, and a gap is formed between adjacent two of the slice units; planarizing tops of the slice units; accomplishing circuits on the slice units and turning the slice units into a plurality of circuited slice units; and forming a plurality of semiconductor chip structures individually with each other by at least breaking down the circuited slice units; wherein a planar size of a corresponding one of the slice units is no less than a planar size of a corresponding one of the semiconductor chip structures, or the planar size of the corresponding one of the slice units is no less than multiple of the planar size of the corresponding one of the semiconductor chip structures.

2. The method of claim 1, wherein in the step of providing the slice units on the process carrier, wherein the substrate is a single-crystal silicon substrate, a poly-crystal silicon substrate, a SOI (silicon on insulator) substrate, a SiC (Silicon Carbide) substrate, a Sapphire substrate, a III-V compound substrate, an II-VI compound substrate, or a compound substrate.

3. The method of claim 1, wherein in the step of providing the slice units on the process carrier, wherein the process carrier is a glass substrate.

4. The method of claim 1, before the step of providing the plural of slice units on the process carrier, further comprising: cutting each of the slice units into a plural of chip units, and holding the outlines of the slice units kept, wherein a planar size of one of the chip units is equal to the planar size of the corresponding one of the semiconductor chip structures.

5. The method of claim 4, before the step of cutting each of the slice units into a plurality of chip units, further comprising: taping a film on a bottom face of each of the slice unit.

6. The method of claim 1, wherein in the step of providing the slice units on the process carrier, wherein the substrate of each of the slice units defines a thickness, which is greater than 0.4 mil (10 nm) or is no greater than 100 μm.

7. The method of claim 1, wherein in the step of forming the semiconductor chip structures, wherein each of the semiconductor chip structures further includes a corresponding part of the process carrier.

8. The method of claim 1, wherein in the step of forming the semiconductor chip structures, wherein the corresponding one of the semiconductor chip structures is a chip with a set of circuits or with a system of integrated circuits.

9. A semiconductor carrier, comprising: a process carrier; and a plurality of slice units connected on a surface of the process carrier and tiled with one another, wherein each of the slice units includes a substrate with an outline, and a gap is formed between adjacent two of the slice units; wherein each of the slice units is made by a wafer, and a coefficient of thermal expansion (CTE) of the process carrier approaches a CTE of the substrate.

10. The semiconductor carrier of claim 9, wherein each of the slice units defines a circumscribed circle sharing a co-center with the wafer.

11. The semiconductor carrier of claim 9, further comprising an adhesive formed between the slice units and the process carrier.

12. The semiconductor carrier of claim 11, wherein the adhesive is made of PI (Polyimide).

13. The semiconductor carrier of claim 9, wherein the process carrier is made of glass.

14. The semiconductor carrier of claim 9, wherein in the step of providing the slice units on the process carrier, wherein the substrate of each of the slice units defines a thickness, which is greater than 0.4 mil or is no greater than 100 μm.

15. The semiconductor carrier of claim 9, wherein the substrate of each of the slice units is a bare substrate.

16. The semiconductor carrier of claim 9, wherein tops of the slice units are planarized.

17. The semiconductor carrier of claim 9, wherein the slice units are accomplished with circuits to be a plurality of circuited slice units.

18. The semiconductor carrier of claim 9, wherein one or more of the circuited slice units include a thin film circuit.

19. The semiconductor carrier of claim 9, wherein one or more of the circuited slice units include a transistor.

20. A semiconductor chip structure formed by turning the circuited slice units as recited in claim 17 into pieces individually with each other.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0072] The disclosure will become more fully understood from the detailed description and accompanying drawings, which are given for illustration only, and thus are not limitative of the present disclosure, and wherein:

[0073] FIG. 1 is a flow chart of a method of fabricating semiconductor chip structures according to an embodiment of this disclosure;

[0074] FIG. 2A is a top view of a semiconductor carrier according to an aspect of this disclosure;

[0075] FIG. 2B is a schematic diagram showing chip units predetermined in the slice unit as shown in FIG. 2A;

[0076] FIG. 3A is a top view of a semiconductor carrier according to another aspect of this disclosure;

[0077] FIG. 3B is a schematic diagram showing chip units predetermined in the slice unit as shown in FIG. 3A;

[0078] FIG. 4A is a top view of a semiconductor carrier according to another aspect of this disclosure;

[0079] FIG. 4B is a schematic diagram showing chip units predetermined in the slice unit as shown in FIG. 4A;

[0080] FIG. 5 is a top view showing slice units tiled with one another on the surface of the process carrier;

[0081] FIG. 6A is a cross-sectional profile of the slice units of FIG. 5 along the line AA, wherein the slice units are arranged on one single adhesive layer; and

[0082] FIG. 6B is a cross-sectional profile of the slice units of FIG. 5 along the line AA, wherein the slice units are arranged on different adhesive layers, respectively.

DETAILED DESCRIPTION OF THE DISCLOSURE

[0083] The present disclosure will be apparent from the following detailed description, which proceeds with reference to the accompanying drawings, wherein the same references relate to the same elements.

[0084] This disclosure relates to a method for fabricating semiconductor chip structures in an effective and efficient manner, including at least four main processes, procedures, or stages. As shown in FIG. 1, the method for fabricating semiconductor chip structures includes the following steps of: (a) providing a plurality of slice units tiled with one another on a surface of a process carrier, wherein each of the slice units is made by a wafer and includes a substrate with an outline, and a gap is formed between adjacent two of the slice units (step S01); (b) planarizing tops of the slice units (step S02); (c) accomplishing circuits on the slice units and turning the slice units into a plurality of circuited slice units (step S03); and (d) forming a plurality of semiconductor chip structures individually with each other by at least breaking down the circuited slice units; wherein a planar size of a corresponding one of the slice units is no less than a planar size of a corresponding one of the semiconductor chip structures, or the planar size of the corresponding one of the slice units is no less than multiple of the planar size of the corresponding one of the semiconductor chip structures (step S04). In some cases, the planar size of a corresponding one of the slice units could equal to the planar size of a corresponding one of the semiconductor chip structures, or the planar size of the corresponding one of the slice units could be multiple of the planar size of the corresponding one of the semiconductor chip structures

[0085] Some aspects and embodiments of this disclosure will be described hereinafter.

[0086] In the step S01, each slice unit 2 is made by a wafer, and the coefficient of thermal expansion (CTE) of the process carrier 1 approaches (or substantially equal to) that of the substrate of the slice unit 2. In one embodiment, the structure of the process carrier 1 and the slice units connected thereon can be realized as a semiconductor carrier SC (as shown in FIGS. 2A, 3A and 4A).

[0087] In the step S01, a plurality of slice units 2 tiled with one another are arranged on a surface of the process carrier 1, and the outline of the substrate of each of the slice units 2 can be rounded or polygon. As shown in FIGS. 2A and 2B, the outline of the substrate of the slice unit 2 is quadrilateral (e.g. square). As shown in FIGS. 3A and 3B, the outline of the substrate of the slice unit 2 is pentagonal. As shown in FIGS. 4A and 4B, the outline of the substrate of the slice unit 2 is hexagonal.

[0088] In one embodiment, the substrate can be, for example but not limited to, a single-crystal silicon substrate, a poly-crystal silicon substrate, a SOI (silicon on insulator) substrate, a IV-IV compound substrate, a Sapphire substrate, a III-V compound substrate, an II-VI compound substrate, or a compound substrate. For example, the IV-IV compound substrate can be a SiC (Silicon Carbide) substrate. The III-V compound substrate can be a GaAs (Gallium-Arsenide) substrate, a GaN (Gallium Nitride) substrate, an InP (Indium Phosphide) substrate, a GaP (Gallium Phosphide) substrate, a GaSb (Gallium Antimonide) substrate, an InAs (Indium Arsenide) substrate, or an InSb (Indium Antimonide) substrate. The II-VI compound substrate can be a CdTe (Cadmium-Telluride) substrate, a CdS (Cadmium-Sulfide) substrate, a ZnTe (Zinc telluride) substrate, a ZnSe (Zinc Selenide) substrate, or a ZnS (Zinc Sulphide) substrate. The compound substrate can be a CuInSe.sub.2 (CIS, Copper Indium Selenide) substrate or a CIGS (Copper Indium Gallium Selenide) substrate. The materials the mentioned above are options for describing of making the substrate, but not for limited.

[0089] In one embodiment, the process carrier 1 can be, for example but not limited to, a glass substrate. In other embodiments, the process carrier 1 can be made of other material with a CTE approaching (or substantially equal to) that of the selected substrate.

[0090] In one embodiment, the slice units 2 and the process carrier 1 can be bounded directly or indirectly. In one aspect, the slice units 2 and the process carrier 1 can be bounded directly by, for example, an anodic bonding, a fusion bonding, or a direct bonding. In another aspect, the slice units 2 and the process carrier 1 can be bounded indirectly through an intermediate material.

[0091] As mentioned above, in the aspect of indirectly bonding, the slice units 2 and the process carrier 1 can be bounded indirectly by, for example but not limited to, an adhesive bonding, a glass-frit bonding, a low-melting glass bonding, a metal bonding, an eutectic bonding, or a dielectric bonding. To be elaborated, the slice units 2 and the process carrier 1 can be bounded indirectly via an adhesive, metal In (Indium), metal Sn (Tin), or low-melting glasses of SnO—ZnO—P.sub.2O.sub.5. The CTE of the adhesive is close to, preferably as same as, the CTE of the substrate. In addition, the adhesive can be a de-bonding layer, such as for example but not limited to, a PI (Polyimide) material. In practice, the adhesive can be implemented in a vacuum chamber.

[0092] FIG. 5 is a top view showing slice units 2 tiled with one another on the surface of the process carrier 1; FIG. 6A is a cross-sectional profile of the slice units 2 of FIG. 5 along the line AA, wherein the slice units 2 are arranged on one single adhesive layer 3; and FIG. 6B is a cross-sectional profile of the slice units 2 of FIG. 5 along the line AA, wherein the slice units 2 are arranged on different adhesive layers 3, respectively.

[0093] As shown in FIG. 6A, when the slice units 2 and the process carrier 1 are bounded indirectly by an adhesive bonding, the adhesive can form a single adhesive layer 3, which can connect multiple or all of the slice units 2 for indirectly bonding the multiple or all of the slice units 2 to the process carrier 1. As shown in FIG. 6B, when the slice units 2 and the process carrier 1 are bounded indirectly by an adhesive bonding, the adhesive can form a plurality of adhesive layers 3, which can connect the slice units 2 respectively (e.g. in a one-to-one manner) for indirectly bonding the slice units 2 to the process carrier 1.

[0094] In one embodiment, each of the slice units 2 can optionally further include a plurality of chip units 21 predetermined but still hold the outline thereof. As shown in FIGS. 2B, 3B and 4B, each slice unit 2 includes a plurality of predetermined chip units 21, and the outline of the slice unit 2 is still remained. The outline can be, for example but not limited to, a quadrilateral outline (see FIG. 2B), a pentagonal outline (see FIG. 3B), or a hexagonal outline (see FIG. 4B).

[0095] In one embodiment, the outline of the substrate may be defined with a polygon outline, wherein the polygon outline of each of the slice units 2 is quadrilateral, pentagonal, hexagonal, or octagonal, but this disclosure is not limited thereto.

[0096] In one embodiment, as shown in FIGS. 5, 6A and 6B, in the adjacent two of the slice units 2, a straight side of a corresponding one of the slice units 2 neighbors with a straight side of the other one. To be elaborated, the corresponding one of the slice units 2 defines a circumscribed circle sharing a co-center with the wafer, especially the corresponding one of the slice units 2 may equal to or constrained within a circle of a diameter of 6, 8, or 12 inches. The polygon outline of the substrate may be constrained within a diameter of a 6-inch, 8-inch, or 12-inch wafer, while the substrate with the rounded outline may be the 6-inch, 8-inch, or 12-inch wafer per se. To be noted, the size of the wafer is not limited.

[0097] In one embodiment, before or in the step S01, the method further includes a step of cutting each of the slice units 2 and forming the outline from a rounded one to a polygon one. In addition, before the step of cutting each of the slice units 2 into a plurality of chip units 21, the method can further include a step of: taping a film on a bottom face of each slice unit 2.

[0098] In one embodiment, the size of each of the chip units 21 can be optionally equal to the size of each of the semiconductor chip structures or not, and it depends on how the maximum extent of the flexibility of the design and the utilization of the wafer (substrate) is. In this case, the size of each of the chip units 21 is equal to the size of each of the semiconductor chip structures, but this disclosure is not limited thereto.

[0099] In one embodiment, the substrate of each slice unit 2 is of a thickness, greater than 0.4 mil (10 nm) and is not greater than 100 μm. More specifically, the thickness of the substrate of each slice unit 2 can range from 40 nm to 60 nm. For example, the substrate made from the SOI wafer is capable of offering the thickness from 40 nm to 60 nm. In this stage, the slice unit 2 can be formed as the original size of the wafer, or an after-cut size of the wafer. If the planar size of the slice unit 2 can be trimmed to be less than the planar size of the process carrier 1 but greater than the planar size of the semiconductor chip structure, it would accelerate the whole manufacturing process of the semiconductor chip structures and increase the coverage of the effective working area thereof. If the planar size of the slice unit 2 can be trimmed to as same as the planar size of the semiconductor chip structure, it would provide the final size at the beginning of the whole manufacturing process thereof for varieties.

[0100] The method of this embodiment further includes, before the step S01, a step of cutting each of the slice units 2 into a plurality of chip units 21, and holding the outlines of the slice units kept, wherein the planar size of each of the chip units 21 is close to, preferably equal to, the planar size of the corresponding one of the semiconductor chip structures. In other words, the planar size of one of the chip units 21 is no less than the planar size of the corresponding one of the semiconductor chip structures; in general, the planar size of one of the chip units 21 is substantially equal to, for example slightly larger than, the planar size of the corresponding one of the semiconductor chip structures.

[0101] In one embodiment, the size of each of the chip units 21 is equal to the size of each of the semiconductor chip structures. Before or in the step S01, the planar size of the process carrier 1 is equal to the multiple of the planar size of each of the slice units 2 for containing the slice units 2.

[0102] Before, in or after the step S01, the method of this embodiment further includes a step of: grinding the substrate of a corresponding one of the slice units 2.

[0103] The planar size of the substrate of each of the slice units 2 can be optionally equal to one another or not. In one embodiment, the planar size of the substrate of each of the slice units 2 is equal to one another, but this disclosure is not limited thereto.

[0104] In the step S02, referring to FIGS. 5, 6A and 6B, the method of this embodiment further includes a step of: filling a sealing material in the gap G between the adjacent two of the slice units 2.

[0105] In the step S02, the sealing material is, for example but not limited to, a passivation layer 4 as illustrated in FIGS. 5, 6A and 6B.

[0106] In the step S02, the sealing material can be formed on the substrate and between the gap G by a planarization process. In one embodiment, the planarization process can be, for example but not limited to, a Spin-on-Glass (SOG) process or a Spin-on-Dopant (SOD) process. The formed passivation layer 4 can be made of, for example but not limited to, silicon oxynitride (SiOxNy), silicon oxide (SiOx), or/and silicon nitride (SiNx). To be noted, the material of the passivation layer 4 is not limited to the above-mentioned materials. In other embodiments, the passivation layer 4 can be made of, for example but not limited to, Al.sub.2O.sub.3, SiO.sub.2, Ta.sub.2O.sub.5, TiO.sub.2, or Al.sub.2O.sub.3, or any combination of foresaid materials.

[0107] In the step S02, the coefficient of thermal expansion (CTE) of the sealing material is slightly appropriate as, equivalent to, close to, or as same as the CTE of the substrate. Furthermore specifically, the CTE of the sealing material can be selected to meet the glass or SOI wafer. For example, but not limited, the CTE of the sealing material is not greater than 10 ppm/K and not less than 0.01 ppm/K. More specifically, the CTE of the sealing material ranges from 2.5 to 6 ppm/K.

[0108] In the step S02, the method of this embodiment further includes, after the step of filling the sealing material in the gap G, a step of: grinding the top surfaces of the slice units 2 to a coplanar surface defined together. For more details, each of the slice units 2 may have one or more top surfaces, and the coplanar surface defined by all of the slice units 2 can be defined by the topmost surfaces of all of the slice units 2.

[0109] As motioned foresaid, the passivation layer 4 can be applied above the sealing material for covering. When implementation of the grinding step, the passivation layer 4 is kept covering the sealing material while the coplanar surface is formed.

[0110] Before or in the step S03, the substrate of each of the slice units 2 can be a bare substrate without circuits, or a work-in-process substrate with partial circuits.

[0111] In the step S03, the circuited process includes an evaporation process or deposition process, a lithography process, an annealing process, a flattening process, or a doping process, or any combination of foresaid processes or steps. In more details, the deposition process can be, for example but not limited to, Plasma-enhanced chemical vapor deposition (PECVD)), the lithography process (also called optical lithography or UV lithography) at least includes masking, optical exposing and etching, the flattening process can be, for example but not limited to, spin on glass or spin on dopant, and the doping process can be, for example but not limited to, diffusion or ion implantation. In one embodiment, the accomplished circuits can include the thin-filmed traces or/and transistors, but this disclosure is not limited thereto.

[0112] Before or in the step S04, the method of this embodiment further includes a step of: dicing the circuited slice units to define an outline of the semiconductor chip structures by laser treatment with a boundary notch. In one embodiment, the semiconductor chip structures of a corresponding one of the circuited slice units are connected with each other as a whole, and then the whole structure is broken down to the semiconductor chip structures individually. In an optional manner, one of the circuited slice units are directly broken down to form the semiconductor chip structures individually.

[0113] For more details, the outlines of the semiconductor chip structures can be determined with the steps S01 to S04, or even before the step S01. No matter when or how to define the outlines of the semiconductor chip structures, it would go into pieces at the end of the step S04. In addition, the outline of the slice units, defined with multiple of the semiconductor chip structures, is equivalent to the embodiment of this disclosure.

[0114] In the step S04, the planar sizes of the semiconductor chip structures can optionally equal to each other or not. In one embodiment, the planar sizes of the semiconductor chip structures are equal to each other. In other embodiments, the semiconductor chip structures can have different planar sizes. In other embodiments, a part of the semiconductor chip structures has the same planar size, but the other part of the semiconductor chip structures has different planar sizes. This disclosure is not limited.

[0115] In the step S04, the quantity of the circuited chip units is greater than one hundred, or further greater than one thousand.

[0116] In one embodiment, each of the semiconductor chip structure further includes a corresponding part of the process carrier 1, if the process carrier 1 is also cut for breaking within any one of the step S01 to S04. In an alternative embodiment, the step S04 further includes: removing the process carrier 1 from the semiconductor chip structures before the semiconductor chip structures are divided individually, wherein each of the semiconductor chip structure is defined excluding any corresponding part of the process carrier 1.

[0117] In the step S04, the corresponding one or each of the semiconductor chip structures includes a thin-film circuit.

[0118] In the step S04, the corresponding one or each of the semiconductor chip structures includes a transistor, which can be a thin-film transistor (TFT) or/and a Complementary Metal-Oxide-Semiconductor (CMOS) transistor.

[0119] In the step S04, the corresponding one or each of the semiconductor chip structures is a power management intergraded circuit (PMIC). In the step S04, the corresponding one or each of the semiconductor chip structures is a chip with a set of circuits or with a system of integrated circuits.

[0120] In summary, the method for fabricating semiconductor chip structures of this disclosure includes steps of: providing a plurality of slice units, each of which is made by a wafer, on a process carrier; accomplishing circuits on the slice units; and breaking down the circuited slice units to form a plurality of semiconductor chip structures individually with each other. Herein, the planar size of a corresponding one of the slice units is no less than the planar size of the corresponding one of the semiconductor chip structures, or the planar size of the corresponding one of the slice units is no less than multiple of the planar size of the corresponding one of the semiconductor chip structures. In addition, the semiconductor carrier and semiconductor chip structure can be made by the above-mentioned method. Accordingly, the method of this disclosure can fabricate the semiconductor carrier and the semiconductor chip structures in an effective and efficient manner. The present disclosure has the benefit of, but not objective-oriented as, variety of products, budget control of manufacture, requirements meeting of different application.

[0121] Although the disclosure has been described with reference to specific embodiments, this description is not meant to be construed in a limiting sense. Various modifications of the disclosed embodiments, as well as alternative embodiments, will be apparent to persons skilled in the art. It is, therefore, contemplated that the appended claims will cover all modifications that fall within the true scope of the disclosure.