Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate with a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a handle substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates, and the sacrificial substrate is removed. The removal includes performing an etch into the sacrificial substrate until the device layer is reached. Because the device layer is formed by epitaxy and transferred to the handle substrate, the device layer may be formed with a large thickness. Further, because the epitaxy is not affected by the thickness of the insulator layer, the insulator layer may be formed with a large thickness.

An silicon-on-insulator substrate is provided in the present invention, including a handler, a polysilicon trap-rich layer formed on the handler, an oxide layer formed on the polysilicon trap-rich layer and a monocrystalline silicon layer formed directly on the oxide layer, wherein a bonding interface is between the monocrystalline silicon layer and the oxide layer.

A semiconductor wafer and method for manufacturing thereof are provided. The semiconductor wafer includes a handling substrate and a silicon layer over the handling substrate and having a {111} facet at an edge of a top surface of the silicon layer. The a defect count on the top surface of the silicon layer is less than about 15 each semiconductor wafer. The method includes the following operations: a semiconductor-on-insulator (SOI) substrate is provided, wherein the SOI substrate has a handling substrate, a silicon layer over the handling substrate, and a silicon germanium layer over the silicon layer; and the silicon germanium layer is etched at a first temperature with hydrochloric acid to expose a first surface of the silicon layer.

A glass substrate has a compaction of 0.1 to 100 ppm. An absolute value |Δα.sub.50/100| of a difference between an average coefficient of thermal expansion α.sub.50/100 of the glass substrate and an average coefficient of thermal expansion of single-crystal silicon at 50° C. to 100° C., an absolute value |Δα.sub.100/200| of a difference between an average coefficient of thermal expansion α.sub.100/200 of the glass substrate and an average coefficient of thermal expansion of the single-crystal silicon at 100° C. to 200° C., and an absolute value |Δα.sub.200/300| of a difference between an average coefficient of thermal expansion α.sub.200/300 of the glass substrate and an average coefficient of thermal expansion of the single-crystal silicon at 200° C. to 300° C. are 0.16 ppm/° C. or less.

The present application relates to a method for making silicon epitaxy of a FDSOI device, which includes the following steps: providing a semiconductor structure; sequentially forming a first etch stop layer and an etch reaction layer on a surface of the semiconductor structure; performing an etching operation to the etch reaction layer to form a sidewall structure respectively; filling a second etch stop layer in a space between the sidewall structures at the position of the trench; etching the sidewall structures and the first etch stop layer under the sidewall structures to form a groove structure; removing the second etch stop layer and the remaining first etch stop layer; enabling a silicon substrate at the positions of the trench and the groove structure to epitaxially grow upwards to form epitaxial silicon, the epitaxial silicon being in flush with a top silicon layer.

A semiconductor structure includes a substrate, comprising a first doped region; a first dielectric layer, located on the substrate; multiple deep trench capacitors, extending from the first dielectric layer to an inside of the substrate, in which each of the deep trench capacitors penetrates through the first doped region and comprises a serrated inner wall; multiple second doped regions, located in the substrate, in which each of the second doped regions surrounds a bottom of each deep trench capacitor and extends into the first doped region along an outer wall of the deep trench capacitor; and a first metal layer, located on the first dielectric layer and connected with the multiple deep trench capacitors.

A composite substrate is provided in some embodiments of the present disclosure, which includes a substrate, an insulation layer, a first silicon-containing layer and a first epitaxial layer. The insulation layer is disposed on the substrate. The first silicon-containing layer is disposed on the insulation layer, in which the first silicon-containing layer includes a plurality of group V atoms. The first epitaxial layer is disposed on the first silicon-containing layer, in which the first epitaxial layer includes a plurality of group III atoms. A distribution concentration of the group V atoms in the first silicon-containing layer increases as getting closer to the first epitaxial layer, and a distribution concentration of the group III atoms in the first epitaxial layer increases as getting closer to the first silicon-containing layer. A method of manufacturing a composite substrate is also provided in some embodiments of the present disclosure.

A manufacturing method of a semiconductor device includes at least the following steps. A sacrificial substrate is provided. An epitaxial layer is formed on the sacrificial substrate. An etch stop layer is formed on the epitaxial layer. Carbon atoms are implanted into the etch stop layer. A capping layer and a device layer are formed on the etch stop layer. A handle substrate is bonded to the device layer. The sacrificial substrate, the epitaxial layer, and the etch stop layer having the carbon atoms are removed from the handle substrate.

A semiconductor-on-insulator substrate for use in RF applications, such as a silicon-on-insulator substrate, comprises a semiconductor top layer, a buried oxide layer and a passivation layer over a support substrate. In addition, a penetration layer is provided between the passivation layer and the silicon support substrate to ensure sufficient high resistivity below RF features and avoid increased migration of dislocations in the support substrate. RF devices may be fabricated on and/or in such a semiconductor-on-insulator substrate.

The present disclosure, in some embodiments, relates to a semiconductor structure. The semiconductor structure includes a handle substrate having a plurality of bulk macro defects (BMDs). An insulating layer is disposed onto a top surface of the handle substrate. A device layer, including a semiconductor material, is disposed onto the insulating layer. The handle substrate has a first denuded region and a second denuded region that vertically surround a central region of the handle substrate. The central region has a higher concentration of the plurality of BMDs than both the first denuded region and the second denuded region.