SILICON-ON-INSULATOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

Abstract

An silicon-on-insulator substrate is provided in the present invention, including a handler, a polysilicon trap-rich layer formed on the handler, an oxide layer formed on the polysilicon trap-rich layer and a monocrystalline silicon layer formed directly on the oxide layer, wherein a bonding interface is between the monocrystalline silicon layer and the oxide layer.

Claims

1. A silicon-on-insulator substrate, comprising: a handler; a polysilicon trap-rich layer formed on said handler; an oxide layer formed on said polysilicon trap-rich layer; and a monocrystalline silicon layer formed directly on said oxide layer, wherein a bonding interface is between said monocrystalline silicon layer and said oxide layer.

2. The silicon-on-insulator substrate of claim 1, wherein said polysilicon trap-rich layer is a carbon doped polysilicon trap-rich layer or an undoped polysilicon trap-rich layer.

3. The silicon-on-insulator substrate of claim 1, wherein said handler is a silicon wafer or a glass substrate.

4. The silicon-on-insulator substrate of claim 1, wherein a thickness of said monocrystalline silicon layer is 400-1000 Å.

5. The silicon-on-insulator substrate of claim 1, wherein a thickness of said polysilicon trap-rich layer is 3000-20000 Å.

6. The silicon-on-insulator substrate of claim 1, wherein a thickness of said oxide layer is 300-3000 Å.

7. A method of manufacturing a silicon-on-insulator substrate, comprising: forming a polysilicon trap-rich layer on a handler; forming an oxide layer on said polysilicon trap-rich layer; bonding a bulk silicon wafer on said oxide layer; and performing a thinning process and a trimming process to said bulk silicon wafer to form a monocrystalline silicon layer, wherein a bonding interface is between said monocrystalline silicon layer and said oxide layer.

8. The method of manufacturing a silicon-on-insulator substrate of claim 7, further comprising performing a chemical mechanical polishing process to said oxide layer before bonding said bulk silicon wafer.

9. The method of manufacturing a silicon-on-insulator substrate of claim 7, wherein comprising performing a carbon doping process to said polysilicon trap-rich layer.

10. The method of manufacturing a silicon-on-insulator substrate of claim 7, wherein said handler is a silicon wafer or a glass substrate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute apart of this specification. The drawings illustrate some of the embodiments and, together with the description, serve to explain their principles. In the drawings:

[0010] FIGS. 1-3 are cross-sections of a process flow of manufacturing a silicon-on-insulator substrate in accordance with the preferred embodiment of the present invention; and

[0011] FIG. 4 is a cross-section of the silicon-on-insulator substrate in accordance with the preferred embodiment of the present invention.

[0012] It should be noted that all the figures are diagrammatic. Relative dimensions and proportions of parts of the drawings have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments.

DETAILED DESCRIPTION

[0013] Reference will now be made in detail to exemplary embodiments of the invention, which are illustrated in the accompanying drawings in order to understand and implement the present disclosure and to realize the technical effect. It can be understood that the following description has been made only by way of example, but not to limit the present disclosure. Various embodiments of the present disclosure and various features in the embodiments that are not conflicted with each other can be combined and rearranged in various ways. Without departing from the spirit and scope of the present disclosure, modifications, equivalents, or improvements to the present disclosure are understandable to those skilled in the art and are intended to be encompassed within the scope of the present disclosure.

[0014] It should be readily understood that the meaning of “on,” “above,” and “over” in the present disclosure should be interpreted in the broadest manner such that “on” not only means “directly on” something but also includes the meaning of “on” something with an intermediate feature or a layer therebetween, and that “above” or “over” not only means the meaning of “above” or “over” something but can also include the meaning it is “above” or “over” something with no intermediate feature or layer therebetween (i.e., directly on something). Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature relationship to another element (s) or feature (s) as illustrated in the figures.

[0015] As used herein, the term “substrate” refers to a material onto which subsequent material layers are added. The substrate itself can be patterned. Materials added on top of the substrate can be patterned or can remain unpatterned. Furthermore, the substrate can include a wide array of semiconductor materials, such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), etc. Alternatively, the substrate can be made from an electrically non-conductive material, such as a glass, a plastic, or a sapphire wafer.

[0016] As used herein, the term “layer” refers to a material portion including a region with a thickness. A layer can extend over the entirety of an underlying or overlying structure, or may have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and/or can have one or more layer thereupon, thereabove, and/or therebelow. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which contacts, interconnect lines, and/or through holes are formed) and one or more dielectric layers.

[0017] In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. Additionally, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors, but may allow for the presence of other factors not necessarily expressly described, again depending at least in part on the context.

[0018] It will be further understood that the terms “includes,” “including,” “comprises,” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0019] Firstly, please refer to FIGS. 1-3, which are cross-sections of a process flow of manufacturing a silicon-on-insulator substrate in accordance with the preferred embodiment of the present invention. As shown in FIG. 1, the process of present invention starts from a handler 100. In the embodiment, the handler 100 may be a silicon wafer or a glass substrate, preferably a high-resistance silicon substrate with a resistance between 3000 to 20000 Ω.Math.cm, to lower the signal transmission loss and benefit the application of RFIC and mixed signal. Other semiconductor materials like III-V compound semiconductors, silicon carbide (SiC), silicon germanium (SiGe), germanium (Ge) may also be the material of handler 100.

[0020] Refer still to FIG. 1. A trap-rich layer, such as undoped or carbon-doped polysilicon trap-rich layer 102, is formed on the handler 100 to trap charges accumulating in the buried oxide and prevent crosstalk or nonlinear distortion of RF signals. The grain boundary of polysilicon may usually provide rather good trapping states, and possible inner crystallographic defects like dislocations and/or oxidation induced stacking faults (OISF) may also generate trapping states to trap charge carriers and prevent them accumulating along the top surface of handler 100. In the embodiment, the polysilicon trap-rich layer 102 is formed on the surface of handler 100 by deposition method, such as LPCVD, APCVD, PECVD, with a thickness between 3000 to 20000 Å.

[0021] Refer still to FIG. 1. After the polysilicon trap-rich layer 102 is formed, an oxide layer 104 such as a TEOS (tetraethoxysilane) oxide layer is then formed on the surface of polysilicon trap-rich layer 102. In the embodiment of present invention, the oxide layer 104 functions as a buried oxide of SOI substrate and a bonding layer for substrate bonding. In other embodiment, the material of oxide layer 104 may be other organosilanes, such as tetramethylsilane (Si(CH.sub.3).sub.4), tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane (OMCTS), bis(trimethylsilyl)amine (HMDS), triethoxysilane (HSi(OC.sub.2H.sub.5).sub.3), tris(dimethylamino)silane (SiH(N(CH.sub.3).sub.2).sub.3)), or high-k material like aluminum oxide. The oxide layer 104 may be formed on the surface of polysilicon trap-rich layer 102 by deposition method, for example, by plasma enhanced chemical vapor deposition (PECVD), subatmospheric chemical vapor deposition (SACVD), low pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD). A chemical-mechanical polishing (CMP) process may be performed after the oxide layer 104 is formed to thin the oxide layer 104 to a required thickness and provide flat bonding surface with a thickness between 300 to 3000 Å.

[0022] Please refer next to FIG. 2. After the oxide layer 104 is formed, a device substrate 106 is then bonded on the oxide layer 104. In the embodiment of present invention, the device substrate 106 may be a monocrystalline silicon substrate. The flat surface of organosilane-based oxide layer 104 and its hydrophilicity may easily form bondings to bond the device substrate 106 and the polysilicon trap-rich layer 102. The bonding process may include a plasma treatment to activate the bonding surface and a heat treatment with a duration about half an hour to few hours to form stronger bondings. In other embodiment, the device substrate 106 may also use other semiconductor material, such as III-V compound semiconductors, silicon carbide (SiC), silicon germanium (SiGe), germanium (Ge).

[0023] Please refer next to FIG. 3. After the device substrate 106 is bonded on the oxide layer 104, a grinding process is then performed to the device substrate 106 in order to thin the device substrate 106 into a device layer like a monocrystalline silicon layer 106a with a predetermined target thickness, to allow subsequent device stacking and high-density IC package. The grinding process may include coarse grinding, fine grinding and chemical-mechanical polishing (CMP) to thin the monocrystalline silicon substrate with a thickness larger than 50 μm into a monocrystalline silicon layer with a thickness about 400 to 1000 Å. In this way, the manufacture of the SOI substrate in present invention is completed. In this SOI substrate, the monocrystalline silicon layer 106a has lowest resistance and serves as a part of the device layer, while the polysilicon trap-rich layer 102 has highest resistance up to 10.sup.8 Ω.Math.cm. The resistance of handler 100 is high relative to the monocrystalline silicon layer 106a, about 3000 to 20000 Ω.Math.cm.

[0024] Please refer next to FIG. 4, which is a cross-section of the silicon-on-insulator substrate in accordance with the preferred embodiment of the present invention. As shown in figure, the completed SOI substrate in the present invention sequentially include, from bottom to top, the high-resistance handler 100, the polysilicon trap-rich layer 102, the oxide layer 104 (serves as a buried oxide for the SOI substrate) and the monocrystalline silicon layer 106a (thinned device substrate 106), wherein the bonding interface 120 of SOI substrate is between the oxide layer 104 and the monocrystalline silicon layer 106a, which is different from the bonding interface between a buried oxide and a trapping layer in prior art. After the manufacture of SOI substrate is completed, conventional semiconductor FEOL (front-end-of-line) process and BEOL (back-end-of-line) process may then be performed on the surface of monocrystalline silicon layer 106a to form semiconductor devices (not shown) and interconnects like metal interconnection layer 108 and vias 110 in the inter-metal dielectric layer 112.

[0025] It can be understood from the aforementioned embodiment that the features of present invention is using the oxide layer bonding between the device substrate and the handler substrate as the buried oxide for SOI substrate. The bonding interface is between the buried oxide and the device layer, and circuit structures like device layers and metal interconnects are formed on the front side of the substrate after the bonding process. Therefore, it is not necessary to manufacture additional, costly backside contacts and wirings like those did in prior art.

[0026] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.